Method for manufacturing low voltage flash memory

Details Method for manufacturing low voltage flash memory Method for manufacturing low voltage flash memory

2005-08-09

2005-08-09

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S525000

Reexamination Certificate

active

06927128

ABSTRACT:
A memory comprises a gate oxide layer formed on a semiconductor substrate; an ion trap region formed in a corner portion of the gate oxide layer; a floating gate formed on the gate oxide layer; a dielectric layer formed on the floating gate; a control gate formed on the dielectric layer; a spacer provided along side walls of a formed gate; an LDD formed under the spacer on the semiconductor substrate, the LDD being doped at a low concentration with impurities; and a source/drain region formed on an element region of the semiconductor substrate contacting the LDD, the source/drain region being doped at a high concentration with impurities. In one embodiment, the ion trap region is formed by performing ion injection into a corner portion of the gate oxide after the gate, including the control gate and the floating gate, is formed.

REFERENCES:
patent: 5516707 (1996-05-01), Loh et al.
patent: 5750435 (1998-05-01), Pan
patent: 5804496 (1998-09-01), Duane
patent: 5972783 (1999-10-01), Arai et al.
patent: 6225162 (2001-05-01), Lin et al.
patent: 6288433 (2001-09-01), Akram et al.
patent: 6458666 (2002-10-01), Wasshuber

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