Method for manufacturing low breakdown voltage MOS and high brea

Details Method for manufacturing low breakdown voltage MOS and high brea Method for manufacturing low breakdown voltage MOS and high brea

1997-02-26

1999-08-31

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, 438305, 438307, 438291, H01L 218236

Patent

active

059465751

ABSTRACT:
In a semiconductor integrated circuit device having a high breakdown voltage CMOS transistor integrated for programming a programmable element, the present invention is intended to solve a problem of the drain breakdown voltage of the high breakdown voltage transistor going low as a result of a structure that the standard transistor and the high breakdown voltage transistor share common channel dope region. On a P-type monocrystal silicon substrate of 10-20 .OMEGA.cm specific resistivity having a P-well region and a silicon oxide film for separating the elements, a channel dope region for an insulated-gate type field effect transistor A and a channel dope region for an insulated-gate type field effect transistor B are formed separately, making the impurity concentration in one channel dope region two to ten times as high as that in the other channel dope region. By so doing, the characteristics of the two kinds of insulated-gate type field effect transistors may be controlled independently, dispersion in the electrical characteristics of the high breakdown voltage CMOS transistor is suppressed, and the area for the same is made smaller.

REFERENCES:
patent: 5166087 (1992-11-01), Kakimoto et al.
patent: 5296401 (1994-03-01), Mitsui et al.
patent: 5413945 (1995-05-01), Chien et al.

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