Method of fabricating a semiconductor ready-only memory device u

Details Method of fabricating a semiconductor ready-only memory device u Method of fabricating a semiconductor ready-only memory device u

1997-12-18

1999-08-31

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438130, H01L 218246

Patent

active

059465760

ABSTRACT:
A method is provided for fabricating a ROM device for permanent storage of multi-level coded data therein. By the method, an array of MOSFET-based memory cells are first formed on a substrate, each being formed with an island-like gate region and a pair of source/drain regions. In accordance with customer specification, different groups of the memory cells are specified to respectively store a first, a second, a third, and a fourth value of the multi-level coded data. In the mask programming process, a first code-implantation process is performed to implant impurities into the respective channel regions of the second and fourth selected groups of the memory cells so as to vary the threshold voltage thereof. Then, an insulating layer is formed over the wafer, covering all of the memory cells. Next, a second code-implantation process is performed to form a plurality of contact windows in the insulating layer directly above the island-like gates of the first and second selected groups of the memory cells. Then, a conductive layer is deposited over the insulating layer, which fills up all of the contact windows in the insulating layer and is then selectively removed to form a plurality of word lines. This allows the four groups of memory cells to be set to various threshold voltage levels representing the permanent storage of various values of the multi-level coded data.

REFERENCES:
patent: 4356042 (1982-10-01), Gedaly et al.
patent: 4365405 (1982-12-01), Dickman et al.
patent: 5429967 (1995-07-01), Hong
patent: 5585297 (1996-12-01), Sheng et al.

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