Method for manufacturing known good die array having solder bump

Details Method for manufacturing known good die array having solder bump Method for manufacturing known good die array having solder bump

1997-05-12

1999-08-17

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438613, 29593, 257 48, H01L 2166

Patent

active

059406801

ABSTRACT:
A method for manufacturing a known good die array("KGD" array ), which includes the steps of: (a) forming a plurality of circuit patterns, and bonding pads to match solder bumps on a wafer; (b) providing solder bumps on the bonding pads; (c) forming metal layers for wire-bonding on the solder bumps; (d) dividing the wafer having metal layers into respective individual circuit pattern unit dies; (e) holding at least one die in a die holder for testing; (f) wire-bonding circuit contacts of the die holder with the metal layers using wires; (g) testing the die which is electrically interconnected with the die holder; and (h) removing simultaneously the metal layer on the solder bumps for wire bonding and the wires from the die to give a known good die array having solder bumps.

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