Method for manufacturing electronic devices integrated in a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S268000, C438S570000

Reexamination Certificate

active

07871880

ABSTRACT:
A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.

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patent: 2003/0201503 (2003-10-01), Frisina
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patent: 2006/0197152 (2006-09-01), Tokano et al.
patent: 1111685 (2001-06-01), None
Vathulya et al., “Characterization of Inversion and Accumulation Layer Electron Transport in 4H and 6H-SiC MOSFETs on Implanted P-Type Regions,” IEEE Transactions on Electron Devices, vol. 47, No. 11, Nov. 2000, pp. 2018-2023.

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