Method for manufacturing capacitor of semiconductor memory...

Details Method for manufacturing capacitor of semiconductor memory... Method for manufacturing capacitor of semiconductor memory...

2001-05-09

2002-10-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S240000, C438S253000, C438S393000, C438S396000, C438S296000

Reexamination Certificate

active

06472319

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a capacitor including a thermal treatment process for improving the electrical properties of a capacitor.
BACKGROUND OF THE INVENTION
As the integration density of semiconductor memory devices is increased, the space taken up by a memory cell area is typically decreased. A decrease in cell capacitance is typically a serious obstacle to increasing the integration of a dynamic random access memory (DRAM) devices having storage capacitors. A decrease in the cell capacitance not only lowers the ability to read a memory cell and increases a soft error rate, but also makes the operation of a device at low voltage difficult, and makes the power consumption excessive during the operation of a device. Therefore, a method which can increase cell capacitance should be developed for manufacturing a highly integrated semiconductor memory device.
Generally, dielectric properties of the cell capacitance can be evaluated by the equivalent oxide thickness (Toxeq) and the leakage current density. The Toxeq is a value obtained by converting the thickness of a dielectric layer formed of a material other than a silicon oxide substance into the thickness of a dielectric film formed of a silicon oxide substance. As the value of the Toxeq becomes smaller, the capacitance increases. Also, it is preferable that the leakage current density has a small value in order to improve the electrical properties of a capacitor.
For increasing the cell capacitance, research is being done on methods in which a silicon nitride layer or a silicon oxide layer is replaced by a high dielectric layer having a high dielectric constant as a dielectric layer of a capacitor. Accordingly, a dielectric metal oxide, such as Ta
2
O
5
, (Ba, Sr)TiO
3
(BST), Pb(Zr, Ti)O
3
(PZT), is noticed as a strong candidate as a capacitor dielectric layer material for a semiconductor memory device giving a large capacitance.
For manufacturing a capacitor which employs a dielectric layer having a high dielectric constant, generally, a thermal treatment is performed under an atmosphere including oxygen after an upper electrode is formed, in order to improve the leakage current properties and dielectric properties of the capacitor. Thermal treatment improves the leakage current properties of the capacitor, but the temperature of the thermal treatment must be high in order to obtain an effect of satisfactorily improving the leakage current properties. Also, to obtain electrical properties of a satisfactory level, the temperature of the thermal treatment after forming an upper electrode depends on the kind of dielectric layer used and the state of thermal treatment of the dielectric layer.
In order to obtain capacitance of a reasonable level in a semiconductor device which is continuously integrated, a technique of employing a precious material such as Ru and Pt as an electrode material has been developed. For example, in the case where a Ta
2
O
5
layer crystalized under an atmosphere of nitrogen is formed as a dielectric layer, the leakage current properties can be improved only by thermal treatment at a temperature equal to or higher than 500° C. under the atmosphere of oxygen after forming an upper electrode. However, in the case where an Ru layer is formed by a chemical vapor deposition (CVD) method over the Ta
2
O
5
layer as an upper electrode, the upper electrode formed of Ru is oxidized if the temperature of the thermal treatment under the atmosphere of oxygen is equal to or higher than 450° C. after forming the upper electrode, so that it is difficult to perform thermal treatment at a temperature equal to or higher than 450° C. In the case where the Ta
2
O
5
layer is formed as a dielectric layer, an effect of improving the leakage current is very small at a thermal treatment temperature of 400° C.
Also, in the case where a BST layer formed by the CVD method is employed as a dielectric layer, satisfactory electrical properties can be obtained only by thermal treatment at a temperature equal to or higher than 500° C. under the atmosphere of oxygen after forming an upper electrode. However, in the case where an Ru layer is formed as an upper electrode, the Ru layer begins to rapidly oxidize at a temperature of equal to or higher than 450° C., so that it is impossible to perform thermal treatment at a temperature of equal to or higher than 500° C.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method for manufacturing a capacitor of a semiconductor memory device which can effectively improve the electrical properties of a capacitor by restraining the oxidation of an upper electrode without lowering the thermal treatment temperature in order to improve the leakage current properties and dielectric properties of a capacitor.
Accordingly, to achieve the above objective, there is provided a method for manufacturing a capacitor of a semiconductor memory device according to an aspect of the present invention, wherein a lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble material is formed over the dielectric layer. The resultant structure having the upper electrode then undergoes a first thermal treatment under a first atmosphere including oxygen the first temperature which is selected to be within the range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant structure undergoes a second thermal treatment under a second atmosphere without oxygen and at a second temperature which is selected to be within the range of 300-900° C., which is higher than the first temperature.
The lower electrode can be formed of a single layer formed of doped polysilicon, TiN, TaN, WN, W, Pt, Ru, Ir, RuO
2
, or IrO
2
, or a complex layer thereof. The dielectric layer can be formed of a single layer of Ta
2
O
5
, TiO
2
, (Ba, Sr)TiO
3
(BST), StTiO
3
(ST), SiO
2
, Si
3
N
4
, or PbZrTiO
3
(PZT), or a complex layer thereof. The upper electrode can be formed of Ru, Pt, Ir, RuO
2
, or IrO
2
. In the first thermal treatment step, the first atmosphere includes oxygen having a concentration of 0.01-100 volume %. Here, the first atmosphere can include O
2
, N
2
O, or O
3
gas. Also, in the second thermal treatment step, the second atmosphere is an inert gas atmosphere or a high vacuum atmosphere. The first and second thermal treatment steps can be performed in-situ in the same chamber.
A method for manufacturing a capacitor of a semiconductor memory device according to the aspect of the present invention further includes a step of forming a silicon nitride layer which covers the lower electrode after forming the lower electrode. Also, a method for manufacturing a capacitor of a semiconductor memory device according to the aspect of the present invention further includes a step of thermally treating the dielectric layer after forming the dielectric layer. If the dielectric layer is thermally treated under an atmosphere including oxygen, it is thermally treated at a temperature of 200-800° C. If the dielectric layer is thermally treated under an atmosphere without oxygen, it is thermally treated at a temperature of 500-800° C.
In a method for manufacturing a capacitor of a semiconductor memory device according to another aspect of the present invention, a lower electrode is formed on a semiconductor substrate. A dielectric layer formed of a Ta
2
O
5
layer is formed over the lower electrode. The dielectric layer is thermally treated. An upper electrode formed of Ru is formed over the thermally treated dielectric layer. The resultant structure having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen and at a first temperature which is selected to be within a rage of 300-500° C., which is lower than the oxidation temperature of the upper

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