Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-19
2003-12-02
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S398000, C438S255000
Reexamination Certificate
active
06656790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to storage nodes of a capacitor, which realize increased effective surface and enhanced mechanical strength, and a method for manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices such as dynamic random access memories (DRAM) increases, patterns become finer. Accordingly, the pitch of each of the storage nodes of capacitors continues to decrease. However, the capacitance required for driving a semiconductor device does not decrease in proportion to a decrease in the design rule of a semiconductor device due to soft errors. As a result, it has been required to increase the capacitance of a capacitor. In particular, a method for increasing the effective surface area of a capacitor storage node by increasing the height of a cylinder type storage node has been proposed.
FIG. 1
is a cross-sectional view illustrating conventional cylinder type storage nodes. Specifically, bit lines
30
are formed on a semiconductor substrate
10
, and an interlayer insulating layer
40
is formed on the bit lines
30
to cover the bit lines
30
. Here, each of the bit lines
30
may be covered with a protection layer
35
consisting of a spacer and a capping layer in order to perform a self-aligned contact process for patterning the interlayer insulating layer
40
. Next, a buried contact pad
50
is formed through the interlayer insulating layer
40
, and cylinder type storage nodes
70
are formed electrically connected to the buried contact pad
50
. Here, the buried contact pad
50
may be electrically connected to the semiconductor substrate
10
via conductive plugs
25
, and the conductive plugs
25
may be surrounded by a lower insulating layer
20
.
The bottom portions of the storage nodes
70
are supported in a lateral direction by an etching stopper
60
used to stop etching of a mold layer (not shown) for forming the storage nodes
70
. If the height of each of the storage nodes
70
is increased considerably to obtain a sufficient amount of capacitance, the mechanical strength of the storage nodes
70
decreases. In general, the mechanical strength of the storage nodes
70
decreases in proportion to the cube of the height of each of the storage nodes
70
.
Due to the decrease in the mechanical strength of the storage nodes
70
, the storage nodes
70
may collapse or tilt to one side. As a result, a bridge may occur between adjacent storage nodes
70
. The occurrence of a bridge between the adjacent storage nodes
70
may cause the malfunction of a semiconductor device, such as multi-bit or twin bit failure.
Therefore, in order to ensure a sufficient amount of capacitance by increasing the height of each of the storage nodes
70
, it is required to enhance the mechanical strength of the storage nodes
70
, which are three-dimensional.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same which are capable of preventing storage nodes of a capacitor from collapsing or tilting to one side by increasing the mechanical strength of the storage nodes and simultaneously obtaining a considerable amount of capacitance by increasing the heights of the storage nodes.
Accordingly, the invention is directed to a method for manufacturing a semiconductor device and a semiconductor device. In accordance with the manufacturing method of the invention, bit lines and protection layers for covering each of the bit lines are formed on a semiconductor substrate. Conductive contact pads are formed between the bit lines to a height level with the top surfaces of the protection layers. A node supporting layer is formed covering the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. A mold layer is formed on the etching stopper. Opening holes are formed to expose the conductive contact pads by patterning the mold layer, the etching stopper, and the node supporting layer. Storage nodes are formed in the opening holes, the storage nodes having the shape of the profile of the opening holes. The outer walls of the storage nodes positioned above the etching stopper are exposed by removing the exposed mold layer.
Here, the step of forming the conductive contact pads includes: forming an interlayer insulating layer to fill a gap between the bit lines; patterning the interlayer insulating layer to expose the top surface and side walls of each of the protection layers covering the bit lines; forming a conductive layer to be electrically connected to the semiconductor substrate by filling a gap between the side walls of the protection layers with a conductive material; and sequentially planarizing the conductive layer and the interlayer insulating layer to expose the top surface of each of the protection layers. Accordingly, the interlayer insulating layer covers two facing lateral sides of adjacent conductive contact pads, and each of the protection layers forms the other facing lateral sides of adjacent conductive contact pads. Sequentially planarizing the conductive layer and the interlayer insulating layer can be performed by etch back or chemical mechanical polishing (CMP). In one embodiment, the node supporting layer is formed of silicon oxide.
The thickness of the node supporting layer may account for about 20-40% of the thickness of the mold layer.
The step of removing the mold layer preferably stops at the surface of the etching stopper.
The semiconductor device of the invention includes: bit lines and protection layers for covering the bit lines; conductive contact pads formed between the bit lines and level with the top surface of each of the protection layers; storage nodes connected to the conductive contact pads and having exposed inner and outer walls; and a node supporting layer surrounding the bottom portions of the storage nodes and thus supporting the storage nodes.
According to the present invention, storage nodes of a capacitor are prevented from collapsing or tilting to one side by increasing the mechanical strength of the storage nodes. Also, a considerable amount of capacitance is obtained by increasing the heights of the storage nodes. The thickness of the node supporting layer may account for about 20-40% of the height of each of the storage nodes.
REFERENCES:
patent: 6171926 (2001-01-01), Chun et al.
patent: 6458653 (2002-10-01), Jang
patent: 6482696 (2002-11-01), Park
patent: 6500763 (2002-12-01), Kim et al.
patent: 20010056241 (2001-04-01), None
Hwang Yoo-sang
Jang Se-myeong
Jeong Hong-sik
Kim Ki-nam
Mills & Onello LLP
Nguyen Tuan H.
Samsung Electronics Co,. Ltd.
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