Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-13
2002-12-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S672000
Reexamination Certificate
active
06489201
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by using a dual-damascene process in which a wiring is formed while simultaneously filling a contact hole.
2. Description of the Related Art
As multi-layer wiring structures are more widely used in semiconductor memory devices, the aspect ratio of contact holes, i.e., the ratio of the diameter of the hole to its depth, increases so that various kinds of problems, such as a non-planar phenomenon, poor step coverage, shorts caused by residual metal, low yield rate, reduced reliability and the like, occur. In order to solve the above problems, a damascene process has been suggested as a new wiring technique. According to the damascene process, a trench (or a hole) is formed by partially etching an insulating layer, and a conductive layer is deposited such that the trench is completely filled. Excess insulating layer remaining on the insulating layer is removed by performing chemical mechanical polishing (CMP) process thereby forming a wiring in the trench.
In the damascene process, the wiring is engraved in a trench area of the insulating layer. The wiring is mainly formed as a line and space pattern. Recently, a damascene process for forming the wiring while simultaneously filling up a via hole or a contact hole is widely used.
A flash memory device is a kind of an EEPROM (electrically-erasable programmable read only memory) which can electrically erase data at high speed. The flash memory device electrically controls the input and output of data by using an F-N (Fowler-Nordheim) tunneling effect or hot electron injection.
Flash memory devices are typically of the NAND type, in which a plurality of cell transistors are connected in series to form a unit string and the unit strings are connected between a bit line and a ground line in a row, or the NOR type, in which each cell transistor is connected between the bit line and the ground line in a row. The NOR type is adapted for high-speed operation and the NAND type is adapted for high integration.
FIGS. 1A
to
1
E are sectional views showing a method for manufacturing a NAND type flash memory using a conventional dual-damascene process. Referring to
FIG. 1A
, an oxide material is deposited on a semiconductor substrate (not shown) formed with cell transistors having a stacked gate structure and selecting-transistors having a MOS transistor structure, thereby forming an insulating interlayer
16
. Then, the insulating interlayer
16
is etched by performing a photolithography process so that a bit line contact hole
18
is formed. A doped polysilicon layer is deposited on the bit line contact hole
18
and the insulating interlayer
16
. Then, a plasma dry etching process is carried out so as to etch-back the polysilicon layer to expose a surface of the insulating interlayer
16
, thereby forming a bit line plug
20
in the bit line contact-hole
18
.
By performing the plasma etching process, gas in a plasma state is dissociated into ions, electrons and active radicals. The ions, electrons and active radicals are combined with atoms existing in an etching area of the semiconductor substrate and disappear from the surface of the semiconductor substrate while creating new materials. At this time, a local charging occurs at the surface of the insulating interlayer
16
caused by the isotropic flux feature of electrons and the directional flux feature of ions in a plasma sheath, so a damaged layer
21
is formed.
Referring to
FIG. 1B
, silicon oxynitride (SiON) is deposited on the bit line plug
20
and the insulating interlayer
16
by using a plasma-enhanced chemical vapor deposition (PE-CVD) process, thereby forming an etching stop layer
22
. Then, TEOS is deposited on the etching stop layer
22
by using the PE-CVD process to form a bit line insulating layer
24
.
Referring to
FIG. 1C
, a bit line insulating layer pattern
25
and an etching stop layer pattern
23
are formed by etching the bit line insulating layer
24
and the etching stop layer
22
using a photolithography process. The bit line insulating layer pattern
25
isolates adjacent bit lines from each other, and is patterned in the same direction as in the bit line. That is, a bit line wiring area
26
is defined between insulating layer patterns
25
.
Referring to
FIG. 1D
, after exposing the active area formed at a peripheral portion of a memory cell using the photolithography process, the exposed insulating interlayer
16
is etched so as to form a metal contact hole
28
.
Referring to
FIG. 1E
, after performing a cleaning process using hydrofluoric acid (HF) for removing a native oxide film remaining on the bit line plug
20
, a barrier metal layer
30
made of titanium/titanium nitride (Ti/TiN) is deposited on the bit line plug
20
, the metal contact hole
28
, the bit line insulating layer pattern
25
and the insulating interlayer
16
. Then, a tungsten layer
32
having a thickness sufficient for filling up the bit line wiring area
26
and the metal contact hole
28
is deposited on the barrier metal layer
30
.
Thereafter, though it is not illustrated, a bit line connected to the bit line plug
20
and a metal wiring layer for filling up the metal contact hole
28
are formed by removing the tungsten layer
32
to expose the surface of the bit line insulating layer pattern
25
by using the CMP process.
According to the above-mentioned conventional method, when the etch back process is carried out, a plate-shaped defect at an edge of a wafer (shown in
FIG. 2
) is shifted into an inner portion of the wafer so that an error occurs when the photolithography process is carried out. The plate-shaped defect mainly occurs at a fixing portion of the wafer to which a chuck is coupled and a bevel portion of the wafer. The plate-shaped defect, which occurs when the polysilicon etch back process is carried out, is assumed as having occurred at a polysilicon type material. Accordingly, if the plate-shaped defect remains in the wafer, the bit line insulating layer pattern
25
cannot be properly formed in the subsequent process or the metal contact hole
28
cannot be opened.
In addition, the damaged layer
21
is formed on the surface of the insulating interlayer
16
by the polysilicon etch back process and the etching stop layer
22
made of silicon oxynitride is stacked on the damage layer
21
. Therefore, when the HF cleaning process is carried out before the barrier metal layer
28
is deposited, a lateral undercut (circle A of
FIG. 1E
) of the etching stop layer pattern
23
increases at an interfacial surface between the etching stop layer pattern
23
and the insulating interlayer
16
. Sometimes, the etching stop layer pattern
23
is lifted so that the bit line insulating layer pattern
25
falls down.
SUMMARY OF THE INVENTION
To solve the above problems of the prior art, it is a first object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing a plate-shaped defect generated during a polysilicon etch back process and solving a lateral undercut problem of an upper insulating layer.
A second object of the present invention is to provide a method for fabricating a non-volatile memory device capable of forming a bit line while simultaneously filling up a metal contact hole and capable of preventing a plate-shaped defect generated during an etch back process of polysilicon for a bit line plug and solving a lateral undercut problem of an upper insulating layer.
In accordance with the invention, there is provided a method for manufacturing a semiconductor device. In accordance with the method of the invention, a polysilicon layer is deposited on an oxide layer having a contact hole or an opening. The polysilicon layer is etched back such that the polysilicon layer remains only in the contact hole or in the opening. A cleaning process is performed using a first etchant having a similar etching
Gurley Lynne
Mills & Onello LLP
Niebling John F.
Samsung Electronics Co,. Ltd.
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