Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-06-19
2007-06-19
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C257SE21135
Reexamination Certificate
active
10431321
ABSTRACT:
The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep more heavily doped region, disposed laterally within the shallow heavily doped region and vertically within and below the shallow heavily doped region. In an optional feature of the present invention, the method further comprises selectively implanting a second impurity, wherein the doping profile of the deep more heavily doped region is graded.
REFERENCES:
patent: 5308780 (1994-05-01), Chou et al.
patent: 5407852 (1995-04-01), Ghio et al.
patent: 5512506 (1996-04-01), Chang et al.
patent: 5545575 (1996-08-01), Cheng et al.
patent: 5631485 (1997-05-01), Wei et al.
patent: 5646430 (1997-07-01), Kaya et al.
patent: 5670389 (1997-09-01), Huang et al.
patent: 5866448 (1999-02-01), Pradeep et al.
patent: 5960283 (1999-09-01), Sato
patent: 5985727 (1999-11-01), Burr
patent: 6104063 (2000-08-01), Fulford et al.
patent: 6153483 (2000-11-01), Yeh et al.
patent: 6187620 (2001-02-01), Fulford et al.
patent: 6285056 (2001-09-01), Kocon
patent: 6294433 (2001-09-01), Luning
patent: 6297535 (2001-10-01), Gardner et al.
patent: 6368926 (2002-04-01), Wu
patent: 6383883 (2002-05-01), Cheng et al.
patent: 6399973 (2002-06-01), Roberds
patent: 6455362 (2002-09-01), Tran et al.
patent: 6524916 (2003-02-01), Scholer et al.
patent: 6660605 (2003-12-01), Liu
patent: 6723609 (2004-04-01), Yang et al.
patent: 2002/0153559 (2002-10-01), Yeap et al.
Stanley Wolf and Richard N. Tauber, Silicon Processing For The VLSI Era, 1986, Lattice Press, vol. I, pp. 437-442.
Stanley Wolf and Richard N. Tauber, Silicon Process For The VLSI Era, 2000, Lattice Press, Second Edition, pp. 202-206 and 833-834.
Isaac Stanetta
Lebentritt Michael
Spansion LLC
LandOfFree
Method for manufacturing a double bitline implant does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a double bitline implant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a double bitline implant will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3874478