Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-24
2004-09-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S209000
Reexamination Certificate
active
06797553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic semiconductor device and method of fabrication, particularly to voltage threshold adjustment for field effect transistors (FETs), and more particularly to the combination of geometry and multiple gate materials used to establish a total work function for a predetermined threshold voltage during gate fabrication.
2. Description of Related Art
The voltage threshold for a field effect transistor, for example a metal-oxide-semiconductor (MOSFET), is the gate voltage necessary to initiate conduction. Generally, a FET has a significant disadvantage in that the threshold voltage, VT, usually varies with respect to geometry, the channel length L, and the drain bias. In a polysilicon gate FET, the type of doping in the polysilicon of the gate electrode has a large influence on the threshold voltage. The polysilicon is typically heavily doped to achieve low resistivity. The Fermi energy of heavily doped (n-type) polysilicon is close to the energy at the edge of the conduction band of silicon. The work function of a material is the difference between the vacuum energy level and the Fermi energy level of the material. In general, the positive gate voltage of an n-channel device must be larger than some threshold voltage before a conducting channel can be induced. Similarly, the negative gate voltage of a p-channel device must be more negative than some threshold voltage to induce the required positive charge in the channel.
As gate lengths scale below 50 nm, FET scaling becomes limited by the finite depth of the gate control. As the channel length, L, decreases, there is a considerable problem with a diminishing threshold voltage, VT. This effect severely impairs device performance and makes it difficult to design integrated circuits with short channel lengths. This problem with threshold voltage control is not apparent until the channel length approaches submicron levels As very large scale integration (VLSI) processes are used to make FETs, the channel lengths become shorter and the gate oxides become thinner, and a higher doping level under the gate in the channel region is required to provide the desired threshold and subthreshold voltage characteristics. However, dopant diffusion from a gate electrode into an underlying channel region may affect the device parameters of the FET, including the threshold voltage.
Some resolutions to this problem include adjusting the threshold voltage by diffusion, doping polysilicon to different conductivity types, and modifying the gate work function difference. For example, in U.S. Pat. No. 4,786,611 issued to Pfiester on 22 Nov. 1988, entitled, “ADJUSTING THRESHOLD VOLTAGES BY DIFFUSION THROUGH REFRACTORY METAL SILICIDES,” a method for adjusting threshold voltages by diffusing impurities is taught. This adjustment is made relatively late in the fabrication process. A masking step selectively provides blocking elements to prevent the diffusion from occurring in certain FETS.
In U.S. Pat. No. 5,933,721 issued to Hause, et al., on 3 Aug. 1999, entitled, “METHOD FOR FABRICATING DIFFERENTIAL THRESHOLD VOLTAGE TRANSISTOR PAIR,” a dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors.
In U.S. Pat. No. 5,942,786 issued to Sheu, et al., on 24 Aug. 1999, entitled, “VARIABLE WORK FUNCTION TRANSISTOR HIGH DENSITY MASK ROM,” a work function of the gates is selected for each potential transistor, which, in turn, selects the threshold voltage for the transistor. P-type and n-type polysilicon are the different work function materials used as gate materials to selectively produce transistors having different threshold voltages. However, each gate material type is dedicated to a single transistor. No attempt is made to combine different gate materials having different work functions for altering the threshold voltage of an individual transistor. Nor is any attempt made to pattern the geometry of this gate material to accommodate shorter channel lengths and different threshold voltage values for individual transistors on the same wafer using a plurality of gate materials.
By placing gates on multi-sides of the FET channel, numerous researchers have theoretically and experimentally shown improvements in FET performance. As miniaturization continues, the supply voltages are required to be smaller. Thus, the magnitude of the threshold voltage must also decrease. Current designs require a thin channel region, t
si
, on the order of 5-50 nm with gate lengths down to 20-200 nm, and L
g
approximately equal to 24 times t
si
.
For the double-gate PETs where a very thin (<10 nm) silicon channel is utilized, it is possible and desirable to use an undoped silicon channel. However, the threshold voltage of such an FET would be entirely determined by its geometry and the work function of the gate material. It is often desirable to provide a variety of threshold voltages on the same chip for optimal circuit design. The present invention focuses on providing multiple threshold voltages on the same chip. The multiple threshold voltages are provided by different work functions of the gate materials and, importantly, by placing specific geometric restrictions on these materials in their layout to accommodate having these multiple threshold voltages on the same wafer.
Reported techniques for generating a dual-gated structure include simply defining the gate lithographically with high step heights, selective epitaxial growth to form an “air-bridge” silicon structure, and wrap-around gates with vertical carrier transport. However, introducing multiple threshold voltages on the same wafer for very large scale integrated circuit chips requires a defmed geometry of predetermined gate materials in close proximity to one another.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for providing a variety of threshold voltages on the same integrated circuit chip for optimal circuit design that allows for an undoped or lightly doped silicon channel.
It is another object of the present invention to provide a FET and method of making the same that minimizes the silicon channel thickness and the adverse effects of diffusion of high dopant materials.
A further object of the invention is to provide a FET and method of making the same that maintains a geometric relationship between each channel and the work functions or gate materials necessary to establish a threshold voltage.
Yet another object of the present invention is to provide a FET and method of making the same that achieves the desired threshold voltage for thin channel devices, such as those used in VLSI chips.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a FE comprising: a multilayer substrate having a top surface; electrically coupled source regions and electrically coupled drain regions in the substrate; a channel region in the substrate between the source and the drain regions, having a plurality of gate regions there through for controlling current flow through the channel region, the gate regions each comprising a different gate material having an associated work function for the FET; and, the plurality of gate regions situated in a predetermined geometric pattern such that the different gate materials are adjacent to each other.
The multilayer substrate may further comprise: electrical contacts connected to the gate material, the contacts isolated by a silicide layer, a nitride layer, and an oxide layer; and, a boron phosphorous glass isolation layer.
The
Adkisson James W
Ballantine Arne W.
Divakaruni Ramachandra
Johnson Jeffrey B.
Jones Erin C.
Curcio Robert
DeLio & Peterson
Henkler Richard A.
International Business Machines - Corporation
Le Thao P.
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