Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-07-03
1997-05-06
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438222, 438224, 438232, H01L 2170
Patent
active
056270976
ABSTRACT:
A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).
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Lutze Jeffrey
Poon Stephen
Venkatesan Suresh
Motorola Inc.
Pham Long
Tsai Jey
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