Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-13
2007-02-13
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S588000, C438S638000, C438S926000, C438S199000, C257SE27060, C257SE29126, C257SE27108
Reexamination Certificate
active
10936114
ABSTRACT:
A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
REFERENCES:
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6365450 (2002-04-01), Kim
patent: 6410376 (2002-06-01), Ng et al.
patent: 6420279 (2002-07-01), Ono et al.
patent: 6475841 (2002-11-01), Taylor, Jr. et al.
patent: 6475874 (2002-11-01), Xiang et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6531750 (2003-03-01), Chan et al.
patent: 6544873 (2003-04-01), Yeom et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6551913 (2003-04-01), Kim et al.
patent: 6586288 (2003-07-01), Kim et al.
patent: 6617209 (2003-09-01), Chau et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6617212 (2003-09-01), Cho et al.
patent: 6620713 (2003-09-01), Arghavani et al.
patent: 6642131 (2003-11-01), Harada
patent: 6667246 (2003-12-01), Mitsuhashi et al.
patent: 6689675 (2004-02-01), Parker et al.
patent: 6696327 (2004-02-01), Brask et al.
patent: 6696345 (2004-02-01), Chau et al.
patent: 6709911 (2004-03-01), Doczy et al.
patent: 6716707 (2004-04-01), Brask et al.
patent: 6746967 (2004-06-01), Brask et al.
patent: 6770568 (2004-08-01), Brask
patent: 6855605 (2005-02-01), Jurczak et al.
patent: 2001/0023120 (2001-09-01), Tsunashima et al.
patent: 2002/0000623 (2002-01-01), Cho et al.
patent: 2002/0058374 (2002-05-01), Kim et al.
patent: 2002/0086504 (2002-07-01), Park et al.
patent: 2002/0155665 (2002-10-01), Doris et al.
patent: 2002/0187610 (2002-12-01), Furukawa et al.
patent: 2002/0197790 (2002-12-01), Kizilyalli et al.
patent: 2003/0032303 (2003-02-01), Yu et el.
patent: 2003/0045080 (2003-03-01), Visokay et al.
patent: 2003/0143809 (2003-07-01), Hummler
patent: 2003/0211684 (2003-11-01), Guo
patent: 2003/0228744 (2003-12-01), Kohno et al.
patent: 2003/0235942 (2003-12-01), Nakamura et al.
patent: 2003/0235943 (2003-12-01), Trivedi
patent: 2004/0077136 (2004-04-01), Ma et al.
patent: 2004/0108559 (2004-06-01), Sugii et al.
patent: 0 899 784 AZ (1999-03-01), None
patent: 2 358 737 (2001-04-01), None
patent: WO 00/57461 (2000-09-01), None
PCT International Search Report; Application No. PCT/US2005/031499; Filing Date: Feb. 9, 2005.
Polishchuk et al., “Dual Workfunction CMOS Gate Technology Based on Metal Interdiffusion”, www.eesc.berkeley.edu, 1 page, (no date).
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page.
Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages, (no date).
Brask Justin K.
Chau Robert S.
Datta Suman
Doczy Mark L.
Doyle Brian S.
Engineer Rahul D.
Estrada Michelle
LandOfFree
Method for making a semiconductor device that includes a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a semiconductor device that includes a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a semiconductor device that includes a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3888990