Method for machining a semiconductor wafer on both sides in...

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Reexamination Certificate

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C438S691000, C438S959000, C451S041000, C451S028000, C451S060000, C451S063000, C451S269000, C451S287000, C451S290000

Reexamination Certificate

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07541287

ABSTRACT:
A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmaxof less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.

REFERENCES:
patent: 6080048 (2000-06-01), Kotagiri et al.
patent: 6299514 (2001-10-01), Boller
patent: 6454635 (2002-09-01), Zhang et al.
patent: 6458688 (2002-10-01), Wenski et al.
patent: 6793837 (2004-09-01), Wenski et al.
patent: 2001/0047978 (2001-12-01), Wenski et al.
patent: 2002/0077039 (2002-06-01), Wenski et al.
patent: 2002/0115387 (2002-08-01), Wenski et al.
patent: 2002/0187639 (2002-12-01), Hennhofer et al.
patent: 2003/0045089 (2003-03-01), Wenski et al.
patent: 2003/0054650 (2003-03-01), Wenski et al.
patent: 2004/0235402 (2004-11-01), Bjelopavlic et al.
patent: 2005/0124264 (2005-06-01), Tominaga et al.
patent: 2008/0318493 (2008-12-01), Aida
patent: 199 05 737 (2000-08-01), None
patent: 100 07 390 (2000-10-01), None
patent: 102 10 023 (2003-05-01), None
patent: 102 50 823 (2005-02-01), None
patent: 0 197 214 (1986-10-01), None
patent: 0 776 030 (1997-05-01), None
patent: 0 887 152 (1998-12-01), None
patent: 1997-150366 (1997-06-01), None
patent: 10-2005-0055531 (2005-06-01), None
Patent Abstract of Japan corresponding to JP 05-177539.
English Derwent Abstract AN 2004-392663 corresponding to DE 102 50 823 B4.
English Derwent Abstract AN 2003-459230 corresponding to DE 102 10 023 A1.

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