Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-23
2002-12-24
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S001000
Reexamination Certificate
active
06499125
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a method for making a semiconductor integrated circuit easily testable. More particularly, the present invention relates to a method for inserting a test circuit into each of a plurality of functional blocks, of which a semiconductor integrated circuit will be made up and for which associated test data sets are prepared, so as to make the integrated circuit externally testable. The present invention also relates to a method for converting test data prepared for each single functional block into test data of the type making testable an integrated circuit to which a test circuit has been inserted.
In recent years, a multiplicity of functional blocks, each of which is pre-designed to execute its own intended function, are used as building blocks for a semiconductor integrated circuit to design the circuit more efficiently. Each of these functional blocks is sometimes provided with test data representing input and expected (output) values thereof to detect a fault through testing. Examples of the functional blocks include logic circuit blocks, memory circuit blocks and large-scale functional blocks such as IP (intellectual property), VC (virtual core) and core.
In testing a semiconductor integrated circuit consisting of these functional blocks using such test data, test circuits should be inserted into the integrated circuit to make each of these functional blocks externally testable. According to the conventional technique, however, descriptions of the routes associated with each of these functional blocks should be modified manually to insert the test circuit thereto.
Also, to make each functional block externally testable through the test circuit inserted, test data prepared for the functional block should be converted into test data applicable to testing the semiconductor integrated circuit. This test data conversion process is also performed manually according to the conventional technique.
However, as the size of a single functional block has been considerably increasing lately, the number of pins per logic block has also been rising by leaps and bounds to reach several hundreds, several thousands or more. Also, as the case may be, a single semiconductor integrated circuit is sometimes made up of a number of functional blocks as mentioned above. Accordingly, insertion of a test circuit involves the work of drawing up a netlist describing connection routes between the input and output pins of each functional block under test and associated external pins at gate level, for example. In addition, even if each functional block is provided with corresponding test data, that test data should be converted into test data adapted to test the semiconductor integrated circuit. As can be seen, if these processes of inserting the test circuit and converting the test data associated with each of these functional blocks are performed manually, then an enormous number of process steps have to be carried out. Thus, the designer is much more likely to commit numerous errors during such overly complicated manual operations.
SUMMARY OF THE INVENTION
A first object of the present invention is inserting test circuits non-manually to make a semiconductor integrated circuit made up of a plurality of functional blocks easily testable.
A second object of the present invention is converting test data prepared for each of the building functional blocks of a semiconductor integrated circuit into test data of the type making the functional blocks in the integrated circuit externally testable.
To achieve the first object, the present invention obtains pin combination information, representing to which input or output pin of a functional block each external pin should be connected, to update routing information contained in existent circuit information.
To achieve the second object, the present invention converts test data associated with each single functional block into test data of the type making the integrated circuit externally testable based on the pin combination information.
Specifically, a first exemplary inserting method according to the present invention is adapted to achieve the first object by inserting a test circuit into an integrated circuit, which is made up of a plurality of functional blocks interconnected, such that test data can be externally input to at least one of the functional blocks when the functional block is tested. The method includes the step of a) obtaining pin allocation information including input and output pin connection information for the at least one functional block under test. The input pin connection information represents which input pin of the functional block should be connected to each external test data input pin. The output pin connection information represents which output pin of the functional block should be connected to each external test data output pin. The method further includes the steps of: b) obtaining machine-readable pin combination information by analyzing the pin allocation information; and c) inserting a test data input circuit between the functional block under test and the external test data input pin or a test data output circuit between the functional block under test and the external test data output pin based on the pin combination information.
According to the first inserting method, pin allocation information, including input and output pin connection information, which represents which input or output pin of the functional block under test should be connected to each external test data input or output pin, is obtained manually or automatically. Then, the pin allocation information is analyzed to obtain machine-readable pin combination information. Thus, information about a testable integrated circuit, including the test circuit (i.e., the test data input or output circuit) applied to the functional block under test, can be obtained without actually designing the test circuit. That is to say, routing information for testing the functional block can be obtained without performing a great deal of modification work manually. As a result, the number of design process steps can be drastically cut down.
A second exemplary inserting method according to the present invention is adapted to achieve the first object by inserting a test circuit into an integrated circuit, which is made up of a plurality of functional blocks interconnected, such that test data can be externally input to at least one of the functional blocks when the functional block is tested. The method includes the step of a) preparing pin allocation information including input and output pin connection information for the at least one functional block under test. The input pin connection information represents which input pin of the functional block should be connected to each external test data input pin. The output pin connection information represents which output pin of the functional block should be connected to each external test data output pin. The method further includes the steps of: b) obtaining routing information by analyzing interconnection routes of the functional block based on information about the integrated circuit; c) obtaining machine-readable pin combination information by analyzing the pin allocation information; and d) inserting a test data input circuit and an input signal direction controller between the external test data input pin and the functional block under test based on the pin combination information. The test data input circuit is used for inputting test data through the external test data input pin to the input pin of the functional block under test in a test mode. The input signal direction controller is provided for enabling the external test data input pin, which functions as an output or bidirectional pin in a normal operation mode, to input the test data in the test mode. The method further includes the step of e) inserting a test data output circuit and an output signal direction controller between the functional block under test and the external test data output pi
Ohta Mitsuyasu
Takeoka Sadami
McDermott & Will & Emery
Tu Christine T.
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