Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-19
2007-06-19
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S121000, C382S144000
Reexamination Certificate
active
10678788
ABSTRACT:
A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.
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Gau Tsai-Sheng
Lin Burn-Jeng
Shin Jaw-Jung
You Jan-Wen
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
Whitmore Stacy A
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