Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-24
2002-06-04
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S738000
Reexamination Certificate
active
06399483
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for improving the contour control of openings created for copper dual damascene structures.
(2) Description of the Prior Art
Semiconductor devices are typically fabricated by the creation of a multiplicity of conductive regions on the surface of a semiconductor substrate. These conductive regions are isolated from each other by dielectric layers. Dielectric layers can contain a large number of materials such as silicon dioxide (“oxide”) or silicon nitride (“nitride”), tetra-ethyl-ortho-silicate (TEOS) based oxides, boro-phosphate-silicate-glass (BPSG), phospho-silicate-glass (PSG), boro-silicate-glass (BSG), oxide-nitride-oxide (ONO), tantalum pentoxide (Ta
2
O
5
), plasma enhanced silicon nitride (PSiNx), titanium oxide, oxynitride, a low dielectric constant material, such as hydrogen silsesquioxane, HDP-FSG (high-density-plasma fluorine-doped silicide glass) is a dielectric that has a lower dielectric constant than regular oxide. Some of the dielectrics, such as silicon dioxides can be grown on the surface of the substrate or can be physically deposited by for instance a sputtering process or by other chemical methods of dielectric deposition. The native properties of a dielectric can further be altered by doping the dielectric layer by either n-type dopants such as arsenic and phosphorous or p-type dopants such as indium or boron. The method of forming the dielectric layer and the doping that is applied to this layer is determined by various device and processing considerations.
To interconnect the various layers of interconnecting conducting lines that are created within the structure of a semiconductor device, openings must be created in the dielectric. These openings are filled with a metal that can contain tungsten, titanium nitride, molybdenum, silicide and polysilicon but typically contains tungsten, wolfram or copper. These openings can be further differentiated between contact openings and via openings. A contact opening is generally defined as an opening made through a layer of dielectric whereby the opening exposes a diffusion region or an opening that is made through a dielectric that has been deposited between a layer of polysilicon and a layer of first level metal. Via openings are generally defined as openings that are created through other layers of oxide such as layers of inter-metal dielectric.
The process of creating an opening starts with the deposition of a layer of dielectric (the dielectric into which the openings are to be made) over which a layer of photoresist is deposited. The layer of photoresist is patterned in accordance with the desired pattern of openings, the photoresist is removed above the layer of dielectric in accordance with the pattern for the to be created openings. The dielectric layer is then etched, that is the dielectric is removed in accordance with the pattern of the openings. A dry etch is typically performed, exposing the dielectric layer to a plasma that is created by using one or more gasses that expose the surface of the oxide where the photoresist has been removed. For etchant gasses, halocarbons or their compounds can be used. Etchants can contain dimethylsulfoxide DMSO or monoethanolamine (MEA). Etching gases are typified by CHF
3
and CF
4
and the energy of incident ions of CFx
+
released therefrom. H
2
can be added to the etching gas. Etchant gasses can contain a mixture of fluorocarbon compounds and a halogen compound. Etchant gasses can also contain carbonyl, thionyl, sulfucyl, nitrosyl, nitryl and C
2
HF
5
. Etchant gasses can further contain SiCl
4
and SiF
4
in combination as a plasma etch. The type of etchant that is applied for a particular step of etching openings will be determined by the processing and functional application of the openings within the overall device structure.
The process of etching is typically defined by etching process control parameters such as the etchant or gas used, the flow rate of the etchant (in sccm), additional etchant gasses used with their flow rate, the gas pressure (expressed in Pa. or Torr), the RF power density applied during the process of etching (for instance 1.8 W/cm
2
at 13.56 MHz), the magnetic field density if used (for instance 1.5×10
−2
T), and the wafer temperature (for instance 0 degrees C.). It is clear that these parameters are highly application dependent and that the particular parameters that are applied during a given process of etching often represent a “best can do” compromise for that process of etching. Increased circuit density often brings with it the need to create openings that have a high aspect ratio. For high aspect ratio openings, it is critical that openings are created that have a profile that allows for complete penetration of the metal that fills the opening while the profile of the opening is such that good adhesion is established between the deposited metal and the sidewalls of the opening. To avoid distortion of the photoresist patterns that are used to create the openings on the dielectric layer, Anti Reflective Coating (ARC) is frequently applied over the surface of the opening. Photolithographic patterning problems can be caused by the increase in use of highly reflective materials such as polysilicon, aluminum, and metal silicides in the creation of the semiconductor device. These materials can cause unwanted reflections from the underlying layers resulting in distortion of the creation of the openings. Anti-reflective coatings (ARC's) are used to minimize the adverse impact due to reflectance from these reflective materials. In many instances, these ARC's are conductive materials which are deposited as a blanket layer on top of metal and simultaneously patterned with the metal to form interconnects. A problem with these ARC's is that many of the metals cannot be used in applications such as dual damascene, wherein the metal layer is not patterned. In a dual damascene application, openings are formed in the interlayer dielectric, and the metal is blanket deposited in those openings and subsequently polished back to form a planar inlaid plug. In such application, the metal layer is never etched and therefore, any conductive ARC a top of the inlaid metal would cause the metal plugs to be electrically short-circuited together through the conductive ARC.
For the creation of the single damascene structure, vias only are created. For the creation of the dual damascene, vias are created and conductors are created above the vias. For the dual damascene, special etch procedures can be used to form both the vias and the conductor patterns in the dielectric layer before the deposition of metal and the metal CMP. A thin etch stop layer can be used for this purpose between two layers of dielectric SiO
2
.
The damascene process first etches the conductor pattern into the dielectric after which the etched pattern is filled with metal to create the buried metalization that also has a surface of good planarity. This damascene process also eliminates the need of a dielectric deposition in order to fill the gaps. A planarized metal deposition process can be used for this to fill the pattern that has been created in a dielectric layer of SiO
2
. An etchback or CMP process will remove the excess metal over the field regions. CMP thereby offers the advantage of providing a globally planarized surface. The indicated processing steps can be applied to both single and dual damascene.
For the dual damascene process, the processing steps can follow three approaches.
Approach 1, the via is created first. The vias are formed by resist patterning after which an etch through the triple layer dielectric stack is performed. This is followed by patterning the conductor in the top layer of SiO
2
thereby using the SiN as an etch stop layer.
Approach 2. The conductor first process. The conductor patterns is formed by resist patterning and by etching the conductor patterns in
Liu Jen-Cheng
Lui Ming-Huei
Tao Hun-Jan
Tsai Chia Shiung
Ackerman Stephen B.
Chaudhuri Olik
Kielin Erik
Saile George O.
Taiwan Semiconductor Manufacturing Company
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