Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-08
2003-04-01
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S108000, C438S612000, C257S779000
Reexamination Certificate
active
06541366
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to flip chip bonding technology and more particularly to improving a solder bump adhesion bond to a UBM contact layer.
BACKGROUND OF THE INVENTION
Packaging of the ULSI chip is one of the most important steps in ULSI manufacturing, contributing significantly to the overall cost, performance and reliability of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies such as chip bonding have become critical. Packaging of the chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction.
As semiconductor device sizes have decreased, the density of devices on a chip has increased along with the size of the chip thereby making chip bonding more challenging. One of the major problems leading to package failure as chip sizes increase is the increasingly difficult problem of thermal coefficient of expansion (TCE) mismatches between materials leading to stress buildup and consequent failure. For example, in flip chip technology chip bonding is accomplished by means of solder bumps formed on under bump metallization (UBM) layers overlying a chip bonding pad where, frequently, improper wetting (bonding) between the solder and UBM layers may lead to a bond not sufficiently strong to withstand such stresses.
In many cases it is necessary to repackage the chip after a package failure requiring costly detachment of the chip from the package and repeating the chip bonding process in a new package. Some chip bonding technologies utilize a solder bump attached to a contact pad (chip bonding pad) on the chip to make an electrical connection from the chip devices to the package. For example, C4 (Controlled-Collapse Chip Connection) is a means of connecting semiconductor chips to substrates in electronic packages. C4 is a flip-chip technology in which the interconnections are small solder balls (bumps) on the chip surface. Since the solder balls forms an area array, C4 technology can achieve the highest density scheme known in the art for chip interconnections. The flip chip method has the advantage of achieving the highest density of interconnection to the device with the lowest parasitic inductance.
Solder bumps may be formed by, for example, vapor deposition of solder material over layers of under bump metallization (UBM) formed on the chip bonding pad. In another method, the layers of solder material may deposited by electrodeposition onto a seed layer material deposited over UBM layers formed on the chip bonding pad. In yet another method, solder bumps may be formed by a solder-paste screen printing method using a mask (stencil) to guide the placement of the solder-paste. Typically, after deposition of the solder materials, for example, in layers or as a homogeneous mixture, the solder bump (ball) is formed after removing a photoresist mask defining the solder material location by heating the solder material to a melting point where according to a reflow process a solder ball is formed with the aid of surface tension. Alternatively, a solder bump (column) may be formed within a permanent mask made of photoresist or some other organic resinous material defining the solder bump area over the chip bonding pad.
In an exemplary process for forming a solder bump on a semiconductor chip, reference is made to
FIGS. 1A-1E
representational of a cross sections of an exemplary chip bonding pad an associated UBM layers and solder bump for chip bonding in flip chip technology. For example, with reference to
FIG. 1A
, the process of creating the solder bumps begins after chip bonding pad
10
, for example Cu or Al, formed by vapor deposition has been deposited on the surface of the semiconductor wafer
8
. After the chip bonding pad
10
is formed, a passivation layer
12
of, for example, silicon dioxide (SiO
2
) is formed over the semiconductor device surface excluding a portion overlying the chip bonding pad
10
. Typically, one or more under bump metallization (UBM) layers, e.g.,
14
A of from about 500 Angstroms to about 5000 Angstroms are then deposited over chip bonding pad
10
and a layer of photoresist
16
formed thereover as shown in FIG.
1
B. The UBM layer
14
A may be, for example, a layer of titanium. The photoresist layer is typically from about 10 to about 25 microns high. As shown in
FIG. 1B
, the photoresist layer
16
is photolithographically patterned and developed to form an opening
17
above the contact pad
10
to expose the UBM layer, e.g.,
14
A. Additional UBM layers may be formed within the mask opening
17
by, for example, an electroplating process or vapor deposition process forming e.g., UBM layers
14
B and
14
C in FIG.
1
C. Layers
14
B and
14
C may be for example, layers of copper and nickel, respectively. UBM layers are formed over the chip bonding pad
10
, for example, to allow for better bonding and wetting of the solder material to the uppermost UBM layer adjacent the solder material, e.g.,
14
C, and for protection of the chip bonding pad
10
by the lowermost UBM layer, e.g.,
14
A. A column of solder material
18
A may either be deposited in layers, for example, a layer of Pb followed by a layer of Sn, the solder material layers later being formed into a homogeneous solder during reflow, or may be deposited as a homogeneous solder material by for example vapor deposition or electroplating onto a seed layer (e.g.,
14
C). After removal of the photoresist layer
16
, the UBM layer
14
A is etched through by a reactive ion etch (RIE) process to the underlying passivation layer
12
using the solder column
18
A as an etching mask to protect the underlying UBM layers
14
A,
14
B, and
14
C, as shown in FIG.
1
D. The solder column
18
is then heated to reflow to form a solder bump
18
B over the UBM layer
14
C as shown in FIG.
1
E. After reflow, a homogeneous Pb/Sn solder bump is formed including, for example, with composition ratios indicating weight percent, high lead alloys including 95 Pb/5 Sn (95/5) or 90 Pb/10 Sn (95/10) with melting temperatures in excess of 300° C. or eutectic 63 Pb/37 Sn (63/37) with a melting temperature of 183° C. The solder bump forms a homogeneous material and has a well defined melting temperature. For example, the high melting Pb/Sn alloys are reliable bump metallurgies which are particularly resistant to material fatigue.
A series of layers may be advantageously used to form the UBM layers. The uppermost UBM layer adjacent the solder bump supplies a wettable layer during reflow for the solder bump subsequently formed thereover. For example, some UBM systems to form the plurality of UBM layers may include, reciting the lowermost layer adjacent the chip bonding pad first, chromium and copper (Cr/Cu), titanium and copper (Ti/Cu), and titanium-tungsten (Ti:W/Cu) and copper (Ti:W/Cu), and titanium, copper, nickel (Ti/Cu/Ni). Since conventional bumps melt completely in the reflow soldering process of the flip-chip bonding technique intimately contacting the UBM, the UBM must be able to withstand thermal and mechanical stresses and resist intermetallic phase formations. In conventional solder bumps, the quality of the UBM layers and wettability during reflow is critical to the reliability of the complete assembly. The UBM layers define the size of the solder bump after reflow, provide a surface that is wettable by the solder and that reacts with the solder to provide an adhesion bond preferably with mechanical integrity and thereby acceptable reliability under mechanical and heat stresses. Further, the UBM layers act as a barrier between the semiconductor device and the metals in the interconnection.
One recurring problem with forming a solder bump relates to the wetting behavior of the solder and the UBM layers. For example, preferably, only the major surface of the UBM metal layer adjacent the solder (contact layer) is wetted by the solder during the reflow process and the solder bump is confined to the major surface. In theory, surface tension effects w
Cheng Chia-Jen
Chin Shih-Ming
Liu Fang-Chuang
Yu Hsiu-Mei
Nguyen Dilinh
Pham Long
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
LandOfFree
Method for improving a solder bump adhesion bond to a UBM... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving a solder bump adhesion bond to a UBM..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving a solder bump adhesion bond to a UBM... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3056692