Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-06-23
2002-10-08
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06463560
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the testing of integrated circuits (ICs) and more particularly, to the testing of register-transfer level (RTL) controller-data paths in ICs incorporating built-in self test (BIST) functionality.
2. Description of the Related Art
Integrated circuits (IC) are normally tested both to ensure that the component is defect-free manufactured and/or remains in proper working condition during use. Testing of the IC may for example be accomplished by applying a test pattern to stimulate the inputs of a circuit and monitoring the output response to detect the occurrence of faults. The test patterns may be applied to the circuit using an external testing device. Alternatively, the pattern generator may be a BIST structure comprising part of the internal circuitry of the IC which generates the test patterns.
Although it is desirable when testing the circuit to use exhaustive testing by checking the circuit output response for all possible input permutations, this approach becomes impractical as the number of input variables increases. Thus, a related technique referred to as pseudo-random testing is employed when the number of input variables is so large that it would be burdensome to use an exhaustive testing approach. Because of the relatively low hardware overhead and the simplicity of test pattern generation, pseudo-random testing is the preferred technique for BIST.
With the increasing complexity of integrated circuits, BIST is emerging as a popular testing technique for large and complex designs. BIST has several advantages over other test approaches. For example, since the circuit is tested with pseudo-random test vectors, test generation is no longer needed. Test generation time remains a major bottleneck for gate-level sequential automatic test pattern generation. Also, since the test hardware is integrated into the system in BIST, the circuit can be tested at the operational speed of the circuit, which is not possible in circuits employing either full or partial boundary scan. At-speed testing is important in light of recent work which shows that applying test vectors at the operational speed of the circuit detects more defective integrated circuits than the same test set applied at a slower rate in scan mode. Finally, BIST also has the advantage of allowing field testing of a circuit.
Traditional BIST schemes, however, do suffer from some serious drawbacks. Practical circuits often contain random-pattern resistant faults which result in unacceptable low fault coverage. Thus, the utilization of pseudo-random vectors may not be very good due to the presence of random-pattern resistant faults. In addition, the test (area and delay) overheads tend to be higher than with many other designs for testability schemes. These BIST techniques at the logic level have targeted better test pattern generators, and a reduction in test overheads.
The BIST problem may also be targeted at the register-transfer level (RTL). In view of the drastic reduction in the number of circuit elements needed to perform testing at the RTL, the problem becomes more plausible. At the RTL, there have been some efforts to reduce test overheads by using a testability analysis scheme based on randomness and transparency of modules as described by S. S. K Chiu and C. Papachristou, “A built-in-Self-Testing Approach for Minimizing Hardware Overhead,”
Proc. International Conference on Computer Design,
pp. 282-285, October 1991, which is incorporated herein by reference. A BIST scheme for testing data paths of data-flow intensive RTL circuits was presented in C. Papachristou and J. Carletta, “Test Synthesis in the Behavioral Domain”,
Proc. International test Conference,
pp. 693-702, October 1995, which assumed that both behavioral and RTL information of the circuits are available; in practice, however, this may not be the case.
Other schemes for testing the BIST controller have been presented, as for example by M. Mourani, J. Carletta, and C. Papachristou, “A Scheme for Integrated Controller-Data Path Fault Testing,”
Proc. Design Automation Conference,
pp. 546-551, June 1997. However, in this work the class of circuits is restricted by the requirement that, at most, one multiplexer/bus exists along any register-to-register transfer path. Moreover, the scheme only dealt with register loads and multiplexer select lines coming out of the controller, and did not consider many other types of control lines like ALU select lines, etc. In addition, the complexity of the testability analysis in these schemes is adversely affected by an increase in the bit-width of the data path, thereby limiting their application to small bit-widths. In fact, all experimental results in the above-cited articles are limited to four-bit wide data paths.
Another BIST scheme targeting data paths of data-flow intensive RTL circuits is disclosed in N. Mukherjee, M. Kassab, J. Rajski, and J. Tyszer, “Arithmetic Built-In Self Test for High-Level Synthesis”,
Proc. VLSI Test Symposium,
pp. 132-139, May 1995. This scheme reduced the complexity of testability analysis by concentrating on subspace state coverage. It also reported low area and delay overheads. However, since it relies on arithmetic units for test generation and compaction, its applicability to control-flow intensive circuits is limited. In addition, it does not consider the testability of the combined controller-data path.
SUMMARY OF THE INVENTION
The present invention provides a method for testing RTL controller-data paths in integrated circuits using a BIST scheme without imposing any major design restrictions on the circuit. The only assumption made is that a reset state is present in the controller.
In accordance with the inventive method, a state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules of the RTL circuit within the integrated circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements of the RTL circuit, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. This procedure may add additional test multiplexers to the data path to increase the controllability and observability of the circuit at certain points at which there are testability bottlenecks. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. If possible, these sequences are merged with existing sequences generated for testing other data path elements. This process is then repeated until all RTL elements have been tested.
Once all elements are tested, a BIST controller is synthesized from the stored input sequences. This synthesis includes an analysis of the test environments to detect the occurrence of circular paths. The input and output registers, for which circular paths are not a problem, are converted to pseudo-random pattern generators (PRPGs) and multiple input signature registers (MISRs), respectively. Extra PRPGs and MISRs are instead added along with test multiplexers at the primary input ports and primary output ports of the circuit only. Finally, the circuit is integrated with the BIST components using the determined BIST architecture.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.
REFERENCES:
patent: 5513123 (1996-04-01), Dey et al.
patent: 5731983 (1998-03-01), Balakrishnan et al.
patent: 5748647 (1998-05-01), Bhattacharya et al.
patent: 6237121 (2001-05-01), Yadavalli et al.
“Sequential Test Generati
Bhawmik Sudipta
Ghosh Indradeep
Jha Niraj
Agere Systems Guardian Corp.
Cohen & Pontani, Lieberman & Pavane
De'cady Albert
Harris Cynthia R.
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