Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-04
2001-05-29
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S143000, C438S151000
Reexamination Certificate
active
06238990
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for heat treatment of an SOI wafer, and particularly to a method for heat treatment capable of reducing crystal originated particle (hereinafter referred to as COP) density in the surface of an SOI layer while preventing etching of the SOI layer and a buried oxide layer.
2. Description of the Related Art
There has been proposed a technique such that an SOI (Silicon on Insulator) wafer is heat-treated at 500-1200° C. in a reducing atmosphere of 200 Torr or less in order to improve the surface roughness of the SOI wafer (see Japanese Patent Application Laid-Open (kokai) No. 5-217821). This patent publication states that when an SOI wafer is heat-treated at 950° C. in a hydrogen atmosphere of 80 Torr or less, the surface roughness of the SOI layer is improved from 20 nm to 1.5 nm.
In this case, the SOI layer of the SOI wafer is formed from an epitaxial layer.
Meanwhile, through performing experiments, the inventors of the present invention found that in an SOI wafer whose SOI layer is formed from a silicon wafer produced in accordance with the CZ (Czochralski method), when the SOI wafer undergoes hydrogen annealing at a high temperature of 1150° for a long time of 180 minutes in accordance with the conventional method, silicon of the active layer (SOI layer) of the SOI wafer is etched by an amount of 0.5 &mgr;m and etch pits are formed in a buried oxide layer. They also found that defects such as COPs (Crystals Originated Particles) are present in the SOI layer and that when such defects extend to a substrate oxide film, there occurs a disadvantageous phenomenon such that the COPs remain uneliminated or may even expand and that the buried oxide layer is etched by hydrogen that invades into the oxide layer through defects, resulting in formation of pits and adversely affecting the active layer in the vicinity thereof.
In order to counter the effects of such a phenomenon, the applicant of the present invention has proposed a technique in which heat treatment is performed in a state in which an SOI layer has a thickness greater than 0.5 &mgr;m (see Japanese Patent Application Laid-Open (kokai) No. 10-84100. This method has a drawback of necessity for a step of reducing the thickness of the SOI layer after heat treatment in order to obtain an SOI layer having a thickness of 0.5 &mgr;m or less.
Also, there was proposed a method in which a Si epitaxial layer is grown on a silicon wafer, which is then bonded to another wafer in order to use the epitaxial layer as an SOI layer. This method can reliably eliminate defects but greatly increases production costs.
Further, the above-described hydrogen annealing method is described as requiring at least one hour for high temperature heat treatment, with the result that the productivity is low. Further, since the heat treatment is performed in a batch scheme using a vertical type furnace, a large amount of hydrogen must be caused to flow through the furnace, thereby increasing danger involved in the use of hydrogen.
Meanwhile, presence of COPs has recently been reported to be a cause of decreasing the yield of a device fabricating process. COPs are one kind of crystal defect introduced during crystal growth and are known to have a regular octahedral structure.
When a mirror-polished silicon wafer is cleaned through use of a mixture solution comprising ammonium and hydrogen peroxide, pits are formed on the surface of the wafer. When particles on the thus-cleaned wafer are counted through use of a particle counter, in addition to real particles present on the wafer surface, pits are counted as particles. Such pits are called “COPs” in order to distinguish them from the real particles.
COPs present in the SOI layer of an SOI wafer cause degradation of electrical characteristics of the wafer.
For example, a reliability test which is the important electrical characteristics of a device, especially the time dependent dielectric breakdown (TDDB) of oxide film, relate to COPs, and therefore COPs must be decreased in order to improve TDDB.
Also, COPs are said to affect the time zero dielectric breakdown (TZDB) of oxide film.
Further, COPs are said to adversely affect a device fabrication process. That is, if COPs are present on the surface of an SOI wafer, steps are formed during a wiring process, which causes breakage of wires, resulting in decreased yield.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned problems, and an object of the invention is to provide a method for heat treatment which eliminates COPs in an SOI layer in accordance with a hydrogen annealing method, while preventing etching of the SOI layer and a buried oxide layer; i.e., formation of pits.
Another object of the present invention is to provide a method for heat treatment which improves not only TZDB of oxide film but also other electrical characteristics such as TDDB, and which also improves productivity and decreases an amount of hydrogen gas to be used and production costs.
To achieve the above objects, the present invention provides a method for heat-treating an SOI wafer in a reducing atmosphere, characterized in that the silicon wafer is heat-treated through use of a rapid thermal annealer (RTA) at a temperature within the range of 1100° C. to 1300° C. for 1 sec to 60 sec.
The rapid thermal annealing can be performed by a method in which a wafer is rapidly placed into a heat treatment furnace whose temperature has been set to fall within the above temperature range, and, immediately after the elapse of the above heat treatment time, the wafer is rapidly taken out from the furnace, or a method in which a silicon wafer is brought to a predetermined position within a heat treatment furnace and is then rapidly heated by a heater such as a lamp heater. The description “a wafer is rapidly placed into a heat treatment furnace and is rapidly taken out from the furnace after heat treatment” means that the wafer is placed into the heat treatment furnace and taken out from the furnace, without performance of conventional control in which the temperature of a heat treatment furnace is increased and decreased over a predetermined time or in which the wafer is slowly loaded into and unloaded from the heat treatment furnace. Of course, transferring the wafer to a predetermined position within a furnace takes a certain time, which ranges from several seconds to several minutes depending on the capability of a wafer transfer apparatus.
As described above, when a wafer is quickly heated through use of an RTA in a reducing atmosphere at a higher temperature for a shorter period of time as compared to conventional methods, COPs can be reduced greatly, without an SOI layer or a buried oxide layer being etched, in order to improve not only TZDB of oxide film but also other electrical characteristics such as TDDB.
The heat treatment is preferably performed in an atmosphere of 100% hydrogen or in a mixed gas atmosphere of hydrogen and argon. In this case, COPs are decreased more effectively, while the SOI layer or the buried oxide layer is prevented from being etched.
Further, in the present invention, the heat treatment time can be shortened to 1-30 seconds, which is shorter as compared with the time required for the conventional method. Since the heat treatment is performed at high temperature, COPs can be decreased sufficiently through heat treatment for a period as long as 30 seconds. Further, since the treatment time is short, neither the SOI layer nor the buried oxide layer is etched.
The present invention also provides an SOI wafer that has undergone the heat treatment of the invention. Due to the heat treatment, the COP density of the SOI layer of the SOI wafer decreases from, for example, 10 particles/cm
2
to 0.1 particles/cm
2
. Therefore, there can be obtained an SOI wafer whose SOI layer and buried oxide layer are not etched, so that device characteristics and yield are improved.
In the present invention, an SOI wafer is heat-treated by use of
Aga Hiroji
Kobayashi Norihiro
Mitani Kiyoshi
Hogan & Hartson LLP
Shin-Etsu Handotai & Co., Ltd.
Simkovic Viktor
Tsai Jey
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