Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-25
2004-03-02
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S439000, C438S363000
Reexamination Certificate
active
06699760
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates generally to group III-nitride semiconductors and to methods for fabricating layers of such semiconductors.
2. Discussion of the Related Art
A variety of electronic devices use layers of group III-nitride semiconductors. Herein, group III-nitride semiconductors refer to semiconductors having lattices with primitive cells that include nitrogen and one ore more group III metals. Exemplary of such semiconductors are gallium-nitride (GaN) or aluminum-gallium-nitride (AlGaN).
The manufacture of a layer of group III-nitride semiconductor involves epitaxial growth on a crystalline substrate. In epitaxial growth, the crystalline substrate's lattice controls the initial placement of atoms in the growing layer. Since available crystalline substrates do not have lattices that closely match the lattice of either GaN or AlGaN, epitaxial growth of layers of these group III-semiconductors is presently performed on crystalline substrates with non-matching lattice constants.
FIG. 1
shows a GaN layer
10
that was epitaxially grown on a crystalline substrate
12
with non-matching lattice constants. The mismatch between the lattice constants of the substrate
12
and GaN caused production of lattice defects
14
,
15
in the portion
13
of the GaN layer
10
that initially grew on the substrate
12
. Some of these initial lattice defects
14
subsequently grew through the entire GaN layer
10
. Herein, lattice defects
14
that grow through an entire layer of sequence of layers are known as threading defects.
Threading defects are undesirable in electronic devices, because such defects interfere with carrier transport vertically through and laterally across a layer. In particular, a threading defect often has a higher conductivity than bulk semiconductor and thus, carries more current through a layer than defect-free semiconductor surrounding such a defect. For this reason, a high density of threading defects will partially short out a semiconductor layer so that the conductivity across the layer differs significantly from the conductivity of a bulk semiconductor.
Since densities of threading defects are higher in layers grown on lattice-mismatched crystalline substrates, the negative effects of such defects are more severe in such layers. It is thus, desirable to make layers of group III-nitride semiconductors in which conduction properties are less affected by threading defects.
SUMMARY
In a first aspect, the invention features a method for growing a layer of group III-nitride semiconductor in which the density of threading defects is lower than in conventionally grown semiconductor layers of similar composition. The method includes performing an epitaxial growth of a first layer of group III-nitride semiconductor under growth conditions that cause the growth surface to be rough. The rough growth surface increases the rate at which defects annihilate in pairs during the epitaxial growth and thereby lowers the density of defects that grow through the entire layer to become threading defects. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. Thus, the two-step growth method produces a layer of group III-nitride semiconductor with both a low density of threading defects and a smooth top surface.
In this first aspect, some embodiments provide a specific method for fabricating devices with a layer of a group III-nitride semiconductor that includes gallium. The method includes epitaxially growing a first layer of the semiconductor under gallium-lean growth conditions. The method also includes epitaxially growing a second layer of the semiconductor on the first layer under gallium-rich growth conditions. During the gallium-rich growth, the flow of gallium in an epitaxy gas mixture is greater by, at least, 20 percent than the flow of gallium in the epitaxy gas mixture during the gallium-lean growth.
In a second aspect, the invention features a method for electrically passivating threading defects in layers of group III-nitride'semiconductors. The electrical passivation lowers the conductivity of a defect so that a passivated defect does not carry a higher current density than the surrounding semiconductor matrix. Thus, electrical passivation reduces the effect of threading defects on the conductivity through the layer of group m-nitride semiconductor and thereby reduces defect-induced shorting in such layers.
In the second aspect, various embodiments provide a method for fabricating vertical electronic devices. The method includes epitaxially growing a layer of group III-nitride semiconductor on a crystalline substrate and then, chemically treating an uncovered surface of the layer to selectively electrically passivate defects that thread the layer of semiconductor.
REFERENCES:
patent: 6086673 (2000-07-01), Molnar
patent: 2002/0086534 (2002-07-01), Cuomo et al.
E.J. Miller et al., “Characterization And Local Passivation of Reverse Bias Current Leakage Paths in an AIGaN/GaN Heterostructure, Abstract from Nov. 2001 MRS Fall Meeting, ”Symposium I, Session I10.7 (1 page), publiced online at www.mrs.org/meetings/fall01.*
E.J. Miller et al “Reduction of reverse-bias leakage current in Schottky diodes on GaN grown by molecular-beam epitaxy using surface modification with an atomic force microscope”, Journal of Applied Physics, vol. 91, No. 12, Jun. 15 2002, pp. 9821-9826.
E. J. Miller et al, “Reverse-bias leakage current reduction in GaN Schottky diodes by surface modification with an atomic force microscope”, Abstract from Technical Program Session V of Electronic Materials Conference, Santa Barbara, CA (Jun. 25-27, 2002) 1 page (Note: may have been published before Jun. 25, 2002).
E. J. Miller et al, “Characterization and Local Passivation of Reverse-Bias Current Leakage Paths in an AlGaN/GaN Heterostructure, Abstract from Nov. 2001 MRS Fall Meeting,”, Symposium I, Session I10.7 (1 page), publ.'d online at www.mrs.org/meetings/fall2001/.
Hsu Julia Wan-Ping
Manfra Michael James
Weimann Nils Guenter
Huynh Yennhu
Jr. Carl Whitehead
Lucent Technologies - Inc.
McGabe John F.
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