Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-07
2004-09-28
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
06799292
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for generating a test pattern to identify, by a scan technique, faults (or delays, in particular) that should have been caused in a semiconductor integrated circuit during the fabrication process thereof. The present invention also relates to a method for testing a semiconductor integrated circuit by using the test pattern generated in this manner. More particularly, the present invention is applicable to a fault diagnosis carried out to detect hold errors.
A design rule for semiconductor device processing has been tremendously reduced recently to increase the scale and complexity of a semiconductor integrated circuit steeply, thus making it even more difficult to test such a complicated circuit. To cope with this problem, or to make a semiconductor integrated circuit testable more easily, various techniques, including a scan method, have been developed as means for increasing the testability of a circuit being designed. Thus, it is now possible to identify faults, like those represented as stuck-at fault models, far more efficiently. The capability of detecting a fault supposed as a stuck-at fault model does not depend on the clock frequency. Accordingly, a scan test has normally been carried out at a clock frequency lower than the actual operating frequency of the circuit.
However, the smaller the feature size defined for semiconductor device processing, the more noticeable a process-induced variation. So under the circumstances such as these, it is very hard to test such a complicated circuit reliably enough by the known scan technique that utilizes a low clock frequency. That is to say, a semiconductor integrated circuit now needs to be tested by fully taking a delay into account and using a clock frequency equal to the actual operating frequency of the circuit. A typical example of these new test methods is a pass delay test, which is disclosed in Japanese Laid-Open Publication No. 9-269959, for example.
A path delay test has been performed on a fault model, on which a delay, caused on a signal path, is abnormally long due to a defect occurring during a fabrication process. Specifically, when such a fault happens, a signal, which should normally reach the end point of a signal path within one clock period, cannot arrive there within that period. A fault of this type can usually be identified as a setup error of a flip-flop.
However, no tests have been carried out on a fault model of the opposite type, on which a delay, caused on a signal path, is abnormally short due to a defect occurring during a fabrication process. A fault of this type is usually identifiable as a hold error.
As for a semiconductor integrated circuit subjected to a synchronous design, in particular, the process-induced defect makes the abnormally short delay evident in either of the following two situations. One possibility is (1) that a signal might be unintentionally propagated at a rate much higher than the designed one through a signal path between flip-flops. Or (2) clock lines connected to respective flip-flops might cause skews of variable lengths. When any of these phenomena occurs, a signal cannot be propagated through a path between flip-flops at the intended rate, thus causing a hold error. These two possible factors will be described in further detail with reference to FIG.
12
and
FIGS. 13A through 13C
.
FIG. 12
illustrates part of a semiconductor integrated circuit. As shown in
FIG. 12
, the circuit includes two flip-flops
51
and
52
, combinatorial circuit
53
, signal path
54
, clock lines
55
and
56
and clock tree buffers
57
and
58
. Each of these flip-flops
51
and
52
includes clock input terminal CK, data input terminal D and data output terminal Q.
FIGS. 13A through 13C
are timing diagrams illustrating how the semiconductor integrated circuit shown in
FIG. 12
operates.
FIG. 13A
illustrates a situation where a delay of a normal length is caused on the signal path
54
.
FIG. 13B
illustrates a fault model on which a signal is propagated through the path
54
at a rate higher than the designed one. And
FIG. 13C
illustrates a situation where a skew has been caused between the clock lines
55
and
56
because of the difference in delay.
As shown in
FIG. 13A
, the circuit is designed in such a manner that even a shortest delay that could possibly be caused on the signal path
54
is no shorter than the hold margin of the flip-flop
52
. In addition, the sizes and positions of the clock tree buffers
57
and
58
are adjusted so as to set the clock skew between the clock lines
55
and
56
to (substantially) zero. However, if the signal has unintentionally been propagated through the path
54
faster than expected (i.e., the situation (1)) due to a process-induced variation or defect of the circuit, then the flip-flop
52
causes a hold error, thus making the circuit operating erroneously as shown in FIG.
13
B. Also, even if the delay on the path
54
is of the normal length, a skew might be caused between the clock lines
55
and
56
(i.e., the situation (2)) due to a process-induced variation or defect of the clock tree buffers
57
and
58
or clock lines
55
and
56
. In that case, the flip-flop
52
unintentionally latches the output signal of the flip-flop
51
at the non-original level and operates erroneously as shown in FIG.
13
C.
Accordingly, if such a fault has occurred in any of the signal paths due to the process-induced defects, a test pattern needs to be generated to identify the fault of the signal path.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for generating a test pattern required for identifying such faults on signal paths and a method for testing a semiconductor integrated circuit using a test pattern of this type.
To achieve this object, the present invention generates a test pattern so that a path under test is sensitized and a signal, passing through the path, changes its level while the path is being sensitized.
Specifically, an inventive test pattern generating method for a semiconductor integrated circuit is used to see whether or not a storage device, located at an end point of a path selected from the circuit, will operate erroneously due to a hold error. The test pattern is generated so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a clock signal is input to the storage device.
Another inventive test pattern generating method is applicable to a semiconductor integrated circuit, which includes: at least one external input terminal and at least one external output terminal; a plurality of storage devices; and a combinatorial circuit connected to the external input and output terminals and to the storage devices. The method includes the step of a) generating a signal level transition for a path selected from the combinatorial circuit by assigning an initial value and a changed value, which is an inverted version of the initial value, to start and end points of the path, respectively. In this processing step, output terminals of the combinatorial circuit, which are connected to respective input terminals of the storage devices, are regarded as pseudo-external output terminals. On the other hand, input terminals of the combinatorial circuit, which are connected to respective output terminals of the storage devices, are regarded as pseudo-external input terminals. Also, the start point of the selected path is either the at least one external input terminal or one of the pseudo-external input terminals, while the end point of the selected path is one of the pseudo-external output terminals. The method further includes the step of b) assigning value(s) to the at least one external input terminal and/or at least one of the pseudo-external input terminals and justifying the value(s) so as to sensitize the selected path. And the method further includes the step of c) obtaining, as an expected value, a value justified for the end point of the selected pa
Kajihara Seiji
Reddy Sudhakar M.
Takeoka Sadami
Chaudry Mujtaba
Lamarre Guy J.
McDermott Will & Emery LLP
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