Method for forming transistors with raised source and drains and

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

430314, 430317, 438303, 216 46, G03F 720

Patent

active

061000132

ABSTRACT:
The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

REFERENCES:
patent: 4016587 (1977-04-01), De La Moneda
patent: 4072545 (1978-02-01), De La Moneda
patent: 4404732 (1983-09-01), Andrade
patent: 4688314 (1987-08-01), Weinberg et al.
patent: 4997746 (1991-03-01), Greco et al.
patent: 4998150 (1991-03-01), Rodder et al.
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5198378 (1993-03-01), Rodder et al.
patent: 5213990 (1993-05-01), Rodder
patent: 5243255 (1993-09-01), Iwasaki
patent: 5244759 (1993-09-01), Pierrat
patent: 5275896 (1994-01-01), Garofalo et al.
patent: 5308721 (1994-05-01), Garofalo et al.
patent: 5312768 (1994-05-01), Gonzalez
patent: 5381028 (1995-01-01), Iwasa
patent: 5405795 (1995-04-01), Beyer et al.
patent: 5409853 (1995-04-01), Yu
patent: 5436178 (1995-07-01), Kimura
patent: 5464782 (1995-11-01), Koh
patent: 5486449 (1996-01-01), Hosono et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5573964 (1996-11-01), Hsu et al.
patent: 5610099 (1997-03-01), Stevens et al.
patent: 5741624 (1998-04-01), Jeng et al.
patent: 5981148 (1999-11-01), Brown

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for forming transistors with raised source and drains and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming transistors with raised source and drains and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming transistors with raised source and drains and will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1148667

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.