Metal fusion bonding – Process – Preplacing solid filler
Reexamination Certificate
1999-02-03
2001-01-30
Ryan, Patrick (Department: 1725)
Metal fusion bonding
Process
Preplacing solid filler
C228S174000, C228S180220, C228S248100
Reexamination Certificate
active
06179200
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming solder bumps on an electronic substrate and more particularly, relates to a method for forming solder bumps of improved height on a silicon wafer by reflowing the solder bumps into solder balls in a furnace with the bumps placed in an upside down position.
BACKGROUND OF THE INVENTION
In modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging and interconnecting techniques of such devices. Conventionally, a flip-chip attachment method has been used in the packaging of IC chips. In the flip-chip attachment method, instead of attaching an IC die to a lead frame in a package, an array of solder balls is formed on the surface of the die for the subsequent connection to an outside circuit. When bonding a flip-chip, the IC die is turned upside down and connected to an electronic substrate by reflowing the solder bumps provided on area-array metal terminals on the die to corresponding solder-wettable terminals on the substrate. The flip-chip attachment method offers numerous processing advantages and desirable properties obtained, for instance, the flip-chip interconnects are self-aligning during an IC die/substrate joining, a low lead inductance based on short interconnection lengths, a reduced need for precious metals, a high productivity and a thermal conduction path between the die and the substrate.
A flip-chip bond pad structure consists of multiple thin layers deposited on the bond pads with ball limiting metallurgy (BLM) and solder bumps formed on the BLM layers. The BLM layers are usually multi-layered with an adhesive layer of 0.1 &mgr;m thick, a barrier layer of 1 &mgr;m thick and a bonding layer of 0.3 &mgr;m thick. The solder bumps formed on top of the BLM layers may have diameters ranging between 100 &mgr;m and 250 &mgr;m and a height ranging between 50 &mgr;m and 200 &mgr;m. In the BLM layers, chromium and titanium are commonly used adhesion layer metals, copper, palladium, platinum, nickel are commonly used as barrier layer metals, and gold is commonly used as the bonding layer metal. The solder bump is typically formed of a high-lead content solder that has a high melting temperature.
In fabricating a flip-chip bond structure, the fabrication process requires a tight control of interface processes and manufacturing parameters in order to meet very small dimensional tolerances. Various techniques may be utilized to fabricate a BLM structure and to deposit the solder bump which include evaporation, electroplating, electroless plating and screen printing.
The formation of solder bumps can be carried out by an evaporation method of Pb and Sn through a mask for producing the desired solder bumps. When a metal mask is used, BLM metals and solder materials can be evaporated through designated openings in the metal mask and be deposited as an array of pads onto the chip surface. A typical evaporation process is shown in FIG.
1
.
Referring now to
FIG. 1
, wherein a wafer is first passivated with an insulating layer, via holes are then etched through the wafer passivation layer which is normally SiO
2
to provide a communication path between the chip and the outside circuit. After a molybdenum mask is aligned on the wafer, a direct current sputtering cleans the via openings formed in the passivation layer and removes undesirable oxides. A cleaned via opening assures low contact resistance and good adhesion to the SiO
2
. A chromium layer is then evaporated through a metal mask to form an array of round metal pads each covering an individual via to provide adhesion to the passivation layer and to form a solder reaction barrier to the aluminum pad underneath. A second layer of chromium/copper is then co-evaporated to provide resistance to multiple reflows. This is followed by a final BLM layer of pure copper which forms the solderable metallurgy. A thin layer of gold may optionally be evaporated to provide an oxidation protection layer. These metal-layered pads define the solder wettable regions on the chips which are commonly referred to as the ball limiting metallurgy (BLM). After the completion of BLM, solder evaporation occurs through a metal mask which has a hole diameter slightly greater than the BLM mask-hole diameter. This provides the necessary volume for forming a subsequent solder ball. A solder reflow process is performed at a temperature of about 350° C. to melt and homogenize the evaporated metal pads and to impart a truncated spherical shape to the solder bump. The evaporation method, even though well established and has been practiced for a long time in the industry, is a slow process and thus can not be run at high throughput rate.
A second method for forming solder bumps, the electroplating technique is shown in FIG.
2
. In an electroplating process, BLM layers are first deposited, followed by the deposition of a photoresist layer, the patterning of the photoresist layer, and then the electro-deposition of a solder material into the photoresist openings. After the electro-deposition process is completed, the photoresist layer can be removed and the BLM layers can be etched by using the plated solder bumps as a mask. The solder bumps are then reflowed in a furnace reflow process. The photolithography/electroplating technique is a simpler technique than evaporation and is less expensive because only a single masking operation is required. However, electroplating requires the deposition of a thick and uniform solder over a hole wafer area and etching metal layers on the wafer without damaging the plated solder layer. The technique of electroless plating may also be used to form BLM structure.
One other solder bump formation technique that is capable of solder-bumping a variety of substrates is a solder paste screening technique shown in FIG.
3
. The screen printing technique can be used to cover the entire area of an 8 inch wafer. In the method, a wafer surface covered by a passivation layer with bond pads exposed is first provided. BLM layers are then deposited on top of the bond pads and the passivation layer. After the coating of a photoresist layer and the patterning of the layer, the BLM layers are etched followed by stripping off the photoresist layer. A stencil is then aligned on the wafer and a solder paste is squeegeed through the stencil to fill the openings on top of the bond pads and the BLM layers. After the stencil is removed, the solder bumps may be reflowed in a furnace to form solder balls.
One drawback of the solder paste screen printing process is that, with the recent trend in the miniaturization of device dimensions and the reduction in bump-to-bump spacing (or pitch), the solder paste screening technique becomes impractical. For instance, one of the problems in applying solder paste screening technique to modern IC devices is the paste composition itself. A paste is generally composed of a flux and solder alloy particles. The consistency and uniformity of the solder paste composition becomes more difficult to control with a decreasing solder bump volume. A possible solution for this problem is the utilization of solder paste that contain extremely small and uniform solder particles. However, this can only be achieved at a very high cost penalty. Another problem in using the solder paste screening technique in modern high density devices is the reduced pitch between bumps. Since there is a large reduction in volume from a paste to the resulting solder bump, the screen holes must be significantly larger in diameter than the final bumps. It is therefore generally desirable to form solder bumps that are reflown into solder balls with a larger height and a larger pitch between the balls.
In practicing the flip-chip bonding technology, it has also been found that the fatigue life of the solder ball joint is directly proportional to the height of the solder bumps (or solder balls after reflow). It is therefore desirable to increase the height of the solder balls durin
Hu Hsu-Tien
Kung Ling-Chen
Kuo Chun-Yi
Lu Szu-Wei
Uang Ruoh-Huey
Industrial Technology Research Institute
Pittman Zidia T.
Ryan Patrick
Tung & Associates
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