Method for forming self-aligned dual salicide in CMOS...

Details Method for forming self-aligned dual salicide in CMOS... Method for forming self-aligned dual salicide in CMOS...

2006-09-26

2006-09-26

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S233000, C438S664000, C438S682000

Reexamination Certificate

active

07112481

ABSTRACT:
A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

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U.S. Appl. No. 10/904,885, filed Dec. 2, 2004, entitled “Method for forming Self-aligned Dual Fully Silicided Gates in CMOS”.
U.S. Appl. No. 10/890,753, filed Jul. 14, 2004, entitled “Formation of Fully Silicided Metal Gate Using Dual Self-Aligned Silicide Process”.
U.S. Appl. No. 10/725,851, filed Dec. 2, 2003, entitled “Method for Integration of Silicide Contacts and Silicide Gate metals”.

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