Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-29
2000-08-01
Fourson, George
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438270, 438392, 438561, H01L 218242
Patent
active
060965983
ABSTRACT:
The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form source/drain and bitline diffusion structures for use in pillar memory cells. Additionally, in another embodiment, the present invention is used to form source/drain and plate diffusion structures in pillar memory cells. Both preferred embodiments deposit conformal photoresist on a pillar structure and use an off-axis exposure process to recess a dopant source layer to the proper depth along the pillar. The recessed dopant source layer can then be used to form the source/drain/bitlines diffusions or source/drain/plate diffusions in the pillar memory device.
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Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Rabidoux Paul A.
Abbott Elizabeth
Fourson George
International Business Machines - Corporation
Shkurko Eugene I.
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