Method for forming multi-layered liner on sidewall of node...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S230000, C438S280000, C438S622000, C438S626000, 43, C156S922000

Reexamination Certificate

active

06204107

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates to a method for forming a multi-layered liner on the sidewalls of a node contact opening.
2. Description of Related Art
As semiconductor fabrication moves towards the manufacture of devices having line width under 0.25&mgr;m, width of a word line, a bit line and a contact node opening as well as their distances of separation from each other in DRAM must be reduced according to the design rules. Due to a shorter distance between neighboring bit lines, alignment accuracy of a node contact opening is worse than before. To prevent too much parasitic capacitance between the bit line and the node contact due to lower alignment accuracy, an insulating liner is normally formed on the sidewalls of the node contact opening. In fact, the liner is able to provide the necessary insulation between the subsequently formed node contact and the bit line.
In general, the liner is either a silicon oxide layer or a silicon nitride layer.
FIG. 1
is a schematic, cross-sectional view showing a conventional node contact opening having a liner layer. As shown in
FIG. 1
, the node contact opening structure is built upon a substrate
100
(for simplicity, devices within the substrate
100
are not drawn). The structure includes two dielectric layers
108
and
110
above the substrate
100
, bit lines
106
embedded within the dielectric layer
110
, a node contact opening
102
passing through the dielectric layers
110
and
108
to expose a portion of the substrate
100
, and a liner layer
104
on the sidewalls of the node contact opening
102
. The liner layer
104
is formed by depositing a conformal insulating layer (not shown) over the dielectric layer
110
as well as the interior sidewalls and bottom of the node contact opening
102
. Next, the insulating layer is etched back to remove the insulating layer above the dielectric layer
110
and the insulating layer at the bottom
102
a
of the node contact opening
102
. The remaining insulating layer on the sidewalls of the node contact opening
102
after the etching operation becomes the liner layer
104
.
Although silicon oxide liner
104
can provide good insulation, it can be easily damaged by diluted hydrofluoric acid. Diluted hydrofluoric acid is used for removing native oxide layer above the substrate before the node contact is formed. Therefore, a portion of the silicon oxide of the liner layer
104
may be etched away.
Normally a thicker oxide liner layer is formed to prevent the removal of too much silicon oxide from the liner layer
104
by hydrofluoric acid. However, by so doing, a thicker layer of oxide is also laid over the bottom part
102
a
of the node contact opening
102
. Therefore, time required to etch away the entire oxide layer at the bottom
102
a
of the node contact opening
102
is longer. A longer etching time not only leads to the removal of extra oxide from the top portion
102
b
of the node contact opening
102
, but also leads to the removal of oxide on the sidewall, as well.
Alternatively. silicon nitride can also be used to form the liner layer
104
. Although silicon nitride liner is more resistant to the attack by hydrofluoric acid than silicon oxide liner, silicon nitride tends to have more pinholes. Therefore, the insulation capacity of a silicon nitride layer is inferior. Often, this leads to larger leakage current between the node contact and the bit line
106
resulting in electrical instability problems.
In light of the foregoing, there is a need to improve the liner layer on the sidewalls of a node contact opening.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for forming a multi-layered liner on the sidewalls of a node contact opening so that the corrosion of silicon oxide on the sidewalls of the node contact opening by hydrofluoric acid is minimized.
In another aspect, the invention provides a method for forming a multi-layered liner on the sidewalls of a node contact opening so that leakage current from the node contact to a neighboring bit line due to pin holes in a silicon nitride liner is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a multi-layered liner on the sidewalls of a node contact opening. The method includes the steps of providing a substrate having a dielectric layer thereon, and then forming a node contact opening in the dielectric layer. Next, a first liner layer is formed over the sidewalls of the node contact opening, and then a second liner layer is formed over the first liner layer. A major aspect of this invention is the sequential formation of two or more liner layers on the sidewalls of a node contact opening. The first liner layer has good isolating capacity and very few pin holes so that parasitic capacitance and leakage current due to the relative closeness between the node contact and its neighboring bit line is very much reduced. The second liner layer has strong etching resistance, and therefore is capable of protecting the underlying first liner layer against a corrosive cleaning agent in subsequent cleaning operations.
In one further aspect, the invention also provides a node contact opening having a multi-layered liner structure. The structure includes a substrate, a dielectric layer over the substrate, a node contact opening within the dielectric layer that also exposes a portion of the substrate, a first liner layer on the sidewalls of the node contact opening and a second liner layer over the first liner layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4826786 (1989-05-01), Merenda et al.
patent: 5015592 (1991-05-01), Moldovan
patent: 5663102 (1997-09-01), Park
patent: 5677243 (1997-10-01), Ohsaki
patent: 5700349 (1997-12-01), Tsukamoto et al.
patent: 6060383 (2000-05-01), Nogami et al.

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