Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-27
2002-10-01
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06458653
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2001-674, filed on Jan. 5, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming lower electrodes of a cylinder-shaped capacitor of a memory device or a merged DRAM logic (MDL) device.
2. Description of the Related Art
As the integration density of semiconductor devices increases, design rule decreases. In particular, as a memory device such as a dynamic random access memory (DRAM) rapidly becomes highly-integrated and as its pattern becomes increasingly fine, the pitch between lower electrodes of a capacitor decreases. However, the capacitance required to drive the DRAM does not decrease at the same rate as the pitch decreases because of problems such as soft error.
Consequently, in most DRAMs, a method for making capacitors applied in DRAMs three-dimensional is used to increase the capacitance. Three-dimensional capacitors include pin-shaped capacitors, trench-shaped capacitors, stack-shaped capacitors, and cylinder-shaped capacitors, and among these, the cylinder-shaped capacitor is most widely used.
FIGS. 1 and 2
are sectional views showing a conventional method for forming lower electrodes of a cylinder-shaped capacitor, and
FIG. 3
is a plan view illustrating a conventional method for forming lower electrodes of a cylinder-shaped capacitor. Referring to
FIG. 1
, a lower structure (not shown for simplicity), such as a transistor and a bit line, is formed on a semiconductor substrate
10
, and an interlevel dielectric (ILD) film
12
is deposited on the semiconductor substrate
10
. Buried contacts (BC)
14
as a conductive region connected to the cylinder-shaped capacitor are formed on the semiconductor substrate
10
. Next, a buffer layer
16
and an etch stopper
18
are sequentially formed on the resultant structure.
Next, a sacrificial oxide layer
20
for forming the cylinder-shaped capacitor is formed on the etch stopper
18
. Subsequently, an etching process using a photoresist pattern
22
is performed on the sacrificial oxide layer
20
to form a first opening
24
therein as a region where the cylinder-shaped capacitor is formed.
However, during etching of the sacrificial oxide layer
20
to form the first opening
24
, because etch by-products
26
are formed at the top of the first opening
24
, etch skew (a dotted part of A) in which anisotropic dry etching forms a first opening
24
that is curved instead of straight occurs.
Referring to
FIG. 2
, the etch stopper
18
and the buffer layer
16
are further etched on the semiconductor substrate
10
where the etch skew occurs, and the first opening
24
further extends downwards, thereby exposing an upper part of the BC
14
as a conductive region to be electrically connected to the cylinder-shaped capacitor.
Subsequently, a conductive layer for forming cylinder-shaped lower electrodes
28
is deposited on the semiconductor substrate
10
. Subsequently, a chemical-mechanical polishing (CMP) process is performed on the resultant structure to remove a portion of the conductive layer for forming the cylinder-shaped lower electrodes
28
that is disposed on the sacrificial oxide layer
20
, thereby separating the cylinder-shaped lower electrode
28
. Lastly, the sacrificial oxide layer
20
is removed by wet etching to complete the lower electrodes
28
of the cylindershaped capacitor.
FIG. 3
is a plan view illustrating the cylinder-shaped lower electrodes
28
formed in accordance with the processing steps described above. The left side of
FIG. 3
shows four cylinder-shaped lower electrodes
28
formed on a predetermined region of the semiconductor substrate
10
before integration density increases. The right side of
FIG. 3
, which has the same area as the left side, shows five cylinder-shaped lower electrodes
28
formed on the semiconductor substrate
10
after the integration density has increased. As the integration density increases, the pitch between cylinder-shaped lower electrodes is reduced from t
1
to t
2
, and the probability of twin bit failure increases. In twin bit failure, a bridge between neighboring cylinder-shaped lower electrodes at the top of the cylinder-shaped lower electrodes occurs in proportion to the reduced degree.
The conventional methods for forming a cylinder-shaped capacitor have the following problems.
First, as a memory device such as a DRAM becomes highly-integrated, the number of capacitors formed in a certain area increases. Thus, the spacing between cylinder-shaped lower electrodes decreases, and the probability of twin bit failure increases.
Second, the probability of a bridge occurring between neighboring cylinder-shaped lower electrodes, even at the middle of the cylinder-shaped lower electrodes, increases due to etch skew. Furthermore, as the integration density of a DRAM increases, the height of the cylinder-shaped lower electrodes becomes greater. Thus, the probability of the cylinder-shaped lower electrodes falling down, twin bit failure, or micro-bridge formation, increases.
SUMMARY OF THE INVENTION
To solve the above problems, the present invention contemplates a method for forming a lower electrode of a cylinder-shaped capacitor in which etch skew or twin bit failure can be prevented by applying a slope-improving layer for improving sidewall slope before the formation of the lower electrodes of the capacitor.
Accordingly, according to one embodiment of the present invention, a buffer layer and an etch stopper are sequentially formed on a semiconductor substrate including a conductive region. A sacrificial dielectric layer is formed on the etch stopper. A first opening is formed within the sacrificial oxide layer by etching a portion thereof using the etch stopper. A slope-improving layer for improving sidewall slope of the first opening is formed on the resultant structure. A second opening is then formed by etching a portion of the slope-improving layer, the etch stopper and the buffer layer under the first opening. The second opening exposes the conductive region to which the cylinder-shaped capacitor is electrically connected. A conductive layer for forming cylinder-shaped lower electrodes is deposited on the resultant structure including the second opening. The cylinder-shaped lower electrodes are then formed separated from each other.
According to the present invention, the slope-improving layer for improving sidewall slope having excellent gap-fill characteristics is further formed after the first opening for forming a cylinder-shaped capacitor is formed and improves etch slope of the first opening. Also, the etch profile for a region in which etch skew occurs is improved, and the space between cylinder-shaped lower electrodes is increased, thereby preventing twin bit failure.
REFERENCES:
patent: 6218244 (2001-04-01), Chan et al.
patent: 6232175 (2001-05-01), Liu et al.
patent: 6284595 (2001-09-01), Kato
patent: 6329683 (2001-12-01), Kohyama
Marger & Johnson & McCollom, P.C.
Nguyen Tuan H.
Samsung Electronics Co,. Ltd.
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