Method for forming LDD CMOS using double spacers and large-tilt-

Details Method for forming LDD CMOS using double spacers and large-tilt- Method for forming LDD CMOS using double spacers and large-tilt-

1996-03-28

1998-10-27

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438217, 438227, 438231, 438302, 438303, 438305, 438307, 438525, 257344, 257346, 257369, 257900, H01L 218238

Patent

active

058277471

ABSTRACT:
A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

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