Method for forming LDD CMOS

Details Method for forming LDD CMOS Method for forming LDD CMOS

1997-03-18

2000-02-01

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438302, 438595, H01L 218238

Patent

active

060202319

ABSTRACT:
A method for fabricating a CMOS integrated circuit device with less masking steps than a conventional device. The present method includes a step of providing a semiconductor substrate with a well region, a gate dielectric layer, and a polysilicon gate electrode. The gate dielectric layer is overlying the well region, and the polysilicon gate electrode is overlying the gate dielectric layer. The present method also includes forming a first thermal oxide thickness overlying the polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions. The first thermal oxide thickness is greater than the second thermal oxide thickness, and both layers are defined during the same step. A mask exposes first LDD regions and first source drain regions. The present method then angle implants a first impurity through the first thermal oxide thickness and the second thermal oxide thickness, and implants a second impurity through the second thermal oxide thickness, thereby forming the completed source/drain region in a single masking step.

REFERENCES:
patent: 5413944 (1995-05-01), Lee
patent: 5413945 (1995-05-01), Chien et al.
patent: 5532176 (1996-07-01), Katada et al.

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