Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-01-16
1998-01-20
Dang, Trung
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438240, 438210, 438253, 438256, 438396, 438399, H01L 218242
Patent
active
057100730
ABSTRACT:
The present invention provides a method of manufacturing miniature interconnect for semiconductor devices. The method uses a configuration of spacers and etch barriers (silicon nitride cap layers) to form self aligned source and drain contacts. Antireflective silicon nitride cap layers and highly selective etches are used define smaller interconnect openings. First spacers are formed on the gate electrodes. Later, the second spacers are formed the sidewalls of a storage electrode hole formed in insulation layers over the gate electrodes. The inventive self-aligning process, which uses the two set of spacers, allows a wide processing window for contact etching to form the contact hole and permit a small contact hole aspect ratio. The method reduces the masking steps by defining both the source and drain contacts in the same masking step.
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"CDVSiNx Anti-Reflective Coating for Sub 0.5 .mu.m Lithography" by T. P. Ong et al, 1995, Symposium on VLSI Technology Digest of Technical Papers P73-74.
"Selective Dry Etching in a High Density Plasma for 0.5 .mu.m Complementary Metal-Oxide-Semiconductor Technology" by J. Givens et al, J. Vac.
"High Selectivity Silicon Nitride Etch for Sub-Half Micron Devices" by Karen Reinhard et al, Lam Research Corp. Taiwan Technical.
Jeng Erik S.
Liaw Ing-Ruey
Ackerman Stephen B.
Dang Trung
Saile George O.
Stoffel William J.
Vanguard International Semiconductor Corporation
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