Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-07
2001-10-23
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000
Reexamination Certificate
active
06306700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming semiconductor devices, and more particularly to a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate.
2. Description of the Prior Art
Recently, the demand for semiconductor devices has rapidly increasing due to the usage of a large number of electronic devices. The integrated circuits for computer peripherals, such as output/input circuits or watcher circuits, require a controlling circuit and a driving circuit. In general, low voltage devices are utilized in the controlling circuit, while high voltage devices are utilized in the driving circuit. However, the high/low voltage-integrated devices are also utilized in many other devices, such as an LCD display for a notebook, electronic parts for a watch etc., except for the computer peripherals. Therefore, it is frequent to utilize high/low voltage-integrated devices in semiconductor devices.
FIG. 1A
to
FIG. 1C
show cross-sectional views respectively for various steps of the method for forming a conventional high voltage device according to the current deep-submicron technique. In
FIG. 1A
, firstly, N wells
102
and
104
are formed in the substrate
100
through an N well blank implantation. The N wells
102
and
104
are generally formed by an N type ion implantation, for example, phosphorus or arsenic ion implantation. In
FIG. 1B
, subsequently, a well compensation process is performed to compensate the N well
102
to a P well
106
for an NMOS transistor in the substrate
100
. The well compensation process is performed, utilizing a P type ion implantation, for example, boron ion implantation. For the N type ion implantation, phosphorus or arsenic ion prefers closing to the surface of the N well. While, for the P type ion implantation, boron ion prefers far away from the surface of the P well. Hence, well compensation for the N well
102
compensated to the P well
106
would result in non-uniform concentration distribution for the P well
106
. An additional well compensation is required.
In
FIG. 1C
, a gate oxide layer
108
and a polysilicon gate
110
are formed on the substrate
100
, prior to forming N
−
type doped regions
112
a
and
112
b
. Since the N-grade implantation to form N
−
type doped regions
112
a
and
112
b
is subsequent to the formation of the polysilicon gate
110
, the N
−
type doped regions
112
a
and
112
b
are subject to only one thermal cycle, e.g. an annealing process. Thus, the diffusion depth of the N
−
type doped regions
112
a
and
112
b
is shallow. Moreover, as described in the above, the doped concentration of the compensated P well
106
is not uniform, due to the previous N well blank implantation. Hence, it is difficult to obtain a good doping profile for the snap-back voltage, and therefore, the hot carrier effect is not easily controlled.
Accordingly, it is an intention to find out a method for forming high/low voltage-integrated device to overcome the drawbacks of the conventional device.
It is one object of the present invention to provide a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate, in which a single N well and P well are formed as wells sufficient for a respective high voltage device and a respective low voltage device. Hence, it is not required for well compensation, and the number of masks for ion implantation is decreased.
It is another object of the present invention to provide a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate, in which an N-grade implantation is performed to form N
−
type doped regions in a P well, prior to a gate oxide layer and a polysilicon gate formation. By this method a better doping profile for the snap-back voltage is obtained and the breakdown voltage is increased.
SUMMARY OF THE INVENTION
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate. A substrate is provided. An oxide layer is formed on the substrate. An N well is formed in the substrate. A P well is formed in the substrate opposite to the N well. A plurality of N-field regions are formed as drift regions in the P well and as isolation regions in the N well. A plurality of P-field regions are formed as drift regions in the N well and as isolation regions in the P well region. A plurality of field oxide regions are formed on the N well and the P well in the substrate. N
−
type doped regions are formed in the P well through an N-grade implantation, prior to a gate oxide layer and a polysilicon layer formation. An N
+
type doped region in the N
−
type doped region is formed as a source/drain region for an NMOS transistor in the P well. A P
+
type doped region is formed as a source/drain region for a PMOS transistor in the N well. The polysilicon layer is formed and defined as a gate on the gate oxide layer across a portion of the field oxide region and a portion of the P/N well adjoining thereto.
REFERENCES:
patent: 5424226 (1995-06-01), Vo et al.
patent: 6096589 (2000-08-01), Lee et al.
Owens Beth E.
United Microelectronics Corp.
Zarabian Amir
LandOfFree
Method for forming high voltage devices compatible with low... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming high voltage devices compatible with low..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming high voltage devices compatible with low... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2614758