Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1998-09-15
2001-02-27
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S738000, C257S737000, C257S776000, C257S690000, C257S784000
Reexamination Certificate
active
06194786
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the fabrication of integrated circuits utilizing wire bonding technology in conjunction with arrangements where the bond wires must cross other structures while maintaining clearance to these structures, and typically to the fabrication of integrated circuits having bond wires connected to conductive signal traces provided on a substrate. The signal traces map the interconnections to solder balls or other contact mechanisms formed on the substrate. Typically the integrated circuits are provided in ceramic or plastic packages. The solder balls or other contacts are formed on the substrate to provide a connection to the end users board or system.
BACKGROUND OF THE INVENTION
In producing integrated circuits, one preferred form of packaging is the ball grid array package, or BGA package. In a ball grid array package, an integrated circuit die is provided. Bond wires are used to couple the input and output pads of the integrated circuit die to a substrate. The substrate can be made of a variety of materials, such as ceramic, plastic, BT resin or so called “green board”, fiberglass, tapes, insulating interposers, films, or other suitable insulating materials. The substrate supports traces of conducting material, usually copper or gold or conductive alloy traces that receive bond wires coupled to the integrated circuit bond pads. The traces then couple the signals from the bond wires to solder balls which are, in some BGA package types, formed on the opposite side of the substrate from the side which supports the integrated circuit die. Often throughhole or via type connections are used on the substrate to couple the traces on the integrated circuit side of the substrate to the solder balls formed on the opposite side. The solder balls are coupled to the signal traces on the substrate and provide electrical connections from the outside of the package to the integrated circuit. The cavity containing the integrated circuit is usually filled with a potting material, or alternatively overmolded in a molding press using conventional thermoset or thermoplastic mold compound or resin.
Alternatives to this arrangement are pin grid array or PGA packages, and other similar package types having bond wires coupling an integrated circuit to a substrate or other material. Solder balls are but one material choice for making a contact between the substrate and the end user's board or system, other arrangements may be used as well, such as a direct physical contact between a substrate and the end users board, conductive epoxy, conductive tape, solder dipped leads, etc.
In an improved package type, a “cavity down” package may be used.
FIG. 1
depicts a cross sectional view of such a package. The substrate
11
has a cavity
12
on the bottom side. An integrated circuit die
17
is placed in the cavity upside down, so that the bottom of the integrated circuit die
17
is in physical contact with the substrate
11
, and the bond pads of the die
17
are oriented pointing downwards towards the bottom of the finished package. Next, bond wires
19
are used to couple the input and output bonding pads of the integrated circuit
17
to conductive traces
20
of gold, aluminum, copper or other conductors which are formed on the bottom of the substrate
11
. The signal traces
20
lead to ball receptacle pads (not visible) on the substrate
11
, to which the solder balls
15
are attached. Potting material
23
is then used to cover the die cavity and thus protect the integrated circuit
17
and the bond wires
19
and the signal traces from contamination, particulates, and moisture.
The cavity down package of
FIG. 1
has some advantages over the prior art packages described above. The use of throughhole connections is eliminated because the traces and the solder balls are physically placed on the bottom of the substrate. The substrate is in thermal contact with the bottom of the die, so that if a good thermal conductor is used for the substrate, the package provides excellent thermal performance. Heat sink or fins may be installed on the top of the package for more enhanced thermal performance. These are significant cost and performance advantages over other package types for integrated circuits.
A problem in producing a cavity down integrated circuit package is that the spacing available for the bond wires and the potting material is limited. The vertical distance (labeled “t” in
FIG. 1
) available underneath the package is limited by the diameter of the solder balls. The wires are routed from the bond pads of the integrated circuit to the signal traces on the substrate in such a manner that the wire loop height is placed well within the vertical area “t”, the distance available when the solder balls are attached. This bond wire height requires a looping profile where the top of the loop can not be very high above the substrate surface, causing the wire to be almost parallel with, or at least very close to, the substrate surface.
It is desirable in packaging a high performance integrated circuit to provide conductive power and ground rings to simplify the substrate circuit, and to allow power and ground connections to the die to be added as needed without changing the substrate. This allows the use of different dies in the package without using a different substrate since there are connections for power and ground available all around the cavity. These power and ground rings are placed around the integrated circuit die between the integrated circuit die and the substrate signal traces as shown in
FIG. 2
which is discussed in more detail hereinbelow. The power and ground rings then surround the integrated circuit on all sides. The bond wires have to travel over the rings to reach the substrate signal traces.
However, in packages that require the bonding wires to be almost parallel with the substrate surface, the power or ground rings as known in the prior art cannot be used, because the bond wires pass over and very close to the ground and power rings and can actually short circuit to the power or ground ring. This problem will arise, for example, in making pin grid array packages (“PGA”) and ball grid array packages (“BGA”) using the power and ground rings in the cavity down package of FIG.
1
. Accordingly, a need thus exists for a method and apparatus which provides a reliable wire clearance for bond wires that would otherwise have clearance problems; and for a reliable integrated circuit wire interconnection in packages with ground and/or power rings that have clearance problems between the wire interconnections and the rings.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, a method and apparatus is provided for creating a slight clearance for bond wires which need to cross over conductive traces or other obstacles without physically or electrically contacting the obstacles. In an application of the invention, an integrated circuit is provided in a package with the cavity down, using bond wires almost parallel to the package substrate surface and having at least one wide power ring for providing power or ground voltages to the integrated circuit. A method and apparatus for subsequently forming a package for the completed integrated circuit is provided.
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Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Williams Alexander O.
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