Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-02-27
2001-05-29
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S266000
Reexamination Certificate
active
06238976
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to commonly assigned patent application serial number 08/889,553 (now U.S. Pat. No. 5,936,274 issued Aug. 10, 1999), filed on even date herewith, which disclosure is herein incorporated by reference.
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits, and particularly to floating gate transistor structures for use in nonvolatile semiconductor memories such as in flash EEPROM memory cells.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) are reprogrammable nonvolatile memories that are widely used in computer systems for storing data both when power is supplied or removed. The typical data storage element of an EEPROM is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Data is represented by charge stored on the floating gate and the resulting conductivity obtained between source and drain regions.
Increasing the storage capacity of EEPROM memories requires a reduction in the size of the floating gate transistors and other EEPROM components in order to increase the EEPROM's density. However, memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, the present generation of high density dynamic random access memories (DRAMs), which are capable of storing 256 Megabits of data, require an area of 8F
2
per bit of data. There is a need in the art to provide even higher density memories in order to further increase storage capacity.
SUMMARY OF THE INVENTION
The present invention includes an ultra high density electrically erasable and programmable read only memory (EEPROM) providing increased nonvolatile storage capacity. The memory allows simultaneous erasure of multiple data bits, and is referred to as flash EEPROM. Both bulk semiconductor and semiconductor-on-insulator (SOI) embodiments are included.
In one embodiment of the invention, a memory cell includes a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar includes source/drain and body regions and has a number of sides. More than two floating gates are included in each memory cell. Each gate is associated with a side of the pillar. A number of control gates are also included in each memory cell. Each control gate is associated with a floating gate so as to allow selective storage and retrieval of data on the floating gates. In one embodiment, the control gate is capable of storing more than two charge states on its associated floating gate.
In another embodiment of the invention, a memory cell is fabricated upon a substrate. The memory cell includes a first conductivity type semiconductor pillar. The pillar has top and side surfaces and is formed upon the substrate. A first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate. A second source/drain region, of a second conductivity type, is formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region. A gate dielectric is formed on at least a portion of the side surface of the pillar. More than two floating gates are formed, each of which is substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric. A plurality of control gates are formed, each of which is substantially adjacent to one of the floating gates and insulated therefrom. An intergate dielectric is formed, interposed between each of the substantially adjacent floating and control gates.
In another embodiment of the invention a nonvolatile memory array is fabricated upon a substrate. The memory array includes a plurality of memory cells, each memory cell having a number of floating gate transistors. The memory array also includes a plurality of first gate lines that are substantially parallel in a first direction. Each first gate line interconnects ones of the control gates in ones of the memory cells. A plurality of second gate lines are also formed. The plurality of second gate lines are substantially parallel in a second direction that is substantially orthogonal to the first direction. Each second gate line interconnects ones of the control gates in ones of the memory cells. At least one first source/drain interconnection line is formed at least partially within the substrate. The first source/drain interconnection line interconnects ones of the first source/drain regions of ones of the memory cells. A plurality of data lines is formed. Each data line interconnects ones of the second source/drain regions of ones of the memory cells.
In another embodiment, the present invention provides a method of forming a memory array. The method includes several steps, as described below. A plurality of first conductivity type semiconductor pillars are formed upon a substrate. Each pillar has top and side surfaces. A plurality of first source/drain regions, of a second conductivity type, are formed. Each of the first source/drain regions is formed proximally to an interface between the pillar and the substrate. A plurality of second source/drain regions, of a second conductivity type, is formed. Each of the second source/drain regions is formed within one of the pillars and distal to the substrate and separate from the first/source drain region. A gate dielectric is formed on at least a portion of the side surfaces of the pillars. A plurality of floating gates is formed. Each of the floating gates is formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric. A plurality of control gates is formed. Each of the control gates is formed substantially adjacent to one of the floating gates and insulated therefrom. An intergate dielectric is formed, interposed between ones of the floating gates and ones of the control gates. A plurality of first gate lines is formed. The first gate lines are substantially parallel in a first direction. Each first gate line interconnects ones of the control gates. A plurality of second gate lines are formed, which are substantially parallel in a second direction that is substantially orthogonal to the first direction. Each second gate line interconnects ones of the control gates. At least one first source/drain interconnection line is formed at least partially within the substrate. The first source/drain interconnection line interconnects ones of the first source/drain regions. A plurality of data lines is formed. Each data line interconnects ones of the second/source drain regions.
In one embodiment, the method of forming a memory array on a substrate includes forming a first source/drain layer at a surface of the substrate. A semiconductor epitaxial layer is formed on the first source/drain layer. A second source/drain layer is formed at a surface of the epitaxial layer. A plurality of substantially parallel first troughs are etched, in a first direction, in the epitaxial layer. A first gate dielectric layer is formed substantially adjacent to sidewall regions of the first troughs. A first conductive layer is formed in the first troughs. A portion of the first conductive layer in the first troughs is removed, such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the first gate dielectric layer. A portion of the substrate, underlying a portion of the first troughs and between the floating gate regions, is etched. A first intergate gate dielectric layer is formed on exposed portions of the floating gate regions in the first troughs. First gate lines are formed in the underlying etched portion of the substrate between opposing floating gate regions in the first troughs. Control gate regions are formed in the first troughs between opposing flo
Forbes Leonard
Noble Wendell P.
Bowers Charles
Chen Jack
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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