Method for forming electrically conductive bumps and devices...

Details Method for forming electrically conductive bumps and devices... Method for forming electrically conductive bumps and devices...

2000-08-07

2004-07-27

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S614000, C438S106000

Reexamination Certificate

active

06767818

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for forming electrically conductive bumps and devices formed and more particularly, relates to a single-stencil and single-mask process for forming electrically conductive, compliant bumps on a wafer and devices formed by the method.
BACKGROUND OF THE INVENTION
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions a demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique.
Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
A unique feature of the chip scale package is the use of an interposer layer that is formed of a flexible, compliant material. The interposer layer provides the capability of absorbing mechanical stresses during the package forming steps and furthermore, allows thermal expansion mismatch between the die and the substrate. The interposer layer, therefore, acts both as a stress buffer and as a thermal expansion buffer. Another unique feature of the chip scale package, i.e. such as a micro-BGA package, is its ability to be assembled to a circuit board by using conventional surface mount technology (SMT) processes.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 &mgr;m, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 &mgr;m thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
To achieve the same stress-buffing effect of the interposer layer used in the micro-BGA packages, others have developed similar stress-buffing layers as part of a bump structure in so-called compliant bumps. For instance, in U.S. Pat. Nos. 5,707,902 and 5,393,697, assigned to the common assignee of the present invention and are incorporated herein by reference, methods have been disclosed for fabricating a composite bump structure that includes a polymeric body of relatively low Young's modulus (compared to metals) covered by a conductive metal coating at the input/output pads of an IC (integrated circuit) element or substrate. The composite bump is formed by processing steps of material deposition, photolithography and dry or wet etching techniques. The composite bump can be formed directly on the input/output pad or on a base metal pad which is formed to cover the input/output pad for improved flexibility in locating the composite bump.
A conventional method for forming the composite bump is shown in
FIGS. 1A-1F
. In the method, a semiconductor wafer
10
is first provided. On an active surface
12
of the semiconductor substrate
10
, is then formed a plurality of conductive elements
14
which may be input/output pads for the IC circuits formed on the semiconductor substrate
10
. The plurality of conductive elements
14
is insulated by a passivation layer
16
formed of an insulating material. The passivation layer
16
is first blanket deposited on the active surface
12
of the semiconductor substrate
10
, and then formed photolithographically to expose the plurality of conductive elements
14
, as shown in FIG.
1
A.
In the next step of the process, as shown in
FIG. 1B
, a first electrically conductive material
18
, such as a conductive metal, is blanket deposited on top of the semiconductor substrate
10
overlying the passivation layer
16
and the multiplicity of conductive elements
14
. A suitable metallic material for layer
18
may be aluminum or nickel for providing electrical communication with the plurality of conductive elements
14
. An insulating material layer
20
, possibly of a polymeric-based material, is then coated on the semiconductor substrate
10
encapsulating the first metal layer
18
. The insulating material layer
20
can be advantageously applied onto the semiconductor substrate
10
by a method such as spin coating. When a solvent-containing polymeric material is used for layer
20
, a curing cycle is necessary after the coating process to drive off the residual solvent in the polymeric paste material. It is further preferred that the polymeric material used in layer
20
to be desirably a photosensitive material such that it may be imaged and developed, thus negating the further need for a photoresist layer to be coated on top of the polymeric material layer.
After a photolithographic process is conducted on the polymeric material layer
20
, the layer is dry or wet etched forming a plurality of electrically insulating bumps
22
on top of the first metal layer
18
. It should be noted that during the photolithographic pro

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