Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-12
2001-08-28
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S249000, C438S256000
Reexamination Certificate
active
06281069
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for forming a deep trench capacitor under a shallow trench isolation structure, suitable for use in a dynamic random access memory (DRAM) device.
2. Description of Related Art
As the dimension of semiconductor device is more and more reduced, such as the fabrication generation of 0.15 microns or less, a DRAM device usually would take a deep trench capacitor formed in the semiconductor substrate to provide the memory function. The deep trench capacitor usually is also formed under a shallow trench isolation structure. The deep trench capacitor has already been widely used in the conventional DRAM. However, since the deep trench capacitor is formed under the shallow trench isolation structure, it needs several times of photomask fabrication, so as to performing etching. How to reduce the use of photomask for reducing the complexity in fabrication is a key issue needed to be considered in device design.
FIGS. 1A-1D
are cross-sectional views, schematically illustrating a conventional method to fabricate a deep trench capacitor. In
FIG. 1A
, a substrate
100
is provided. A pad oxide layer
102
, a silicon nitride layer
104
, and a photoresist layer
106
are sequentially formed on the substrate
100
. The photoresist layer
1106
has an opening
102
to expose the silicon nitride layer
104
. Using the opening, the silicon nitride layer
104
, the pad oxide layer
102
and the substrate
100
are etched, whereby a deep trench
107
is formed in the substrate. The deep trench usually is about 7-8 microns.
In
FIG. 1B
, a deep trench capacitor is formed at the lower portion of the deep trench
107
. The deep trench capacitor includes a buried plate
108
diffused into the substrate
100
, a capacitor dielectric
110
, and a polysilicon electrode
112
. An oxide collar
114
is formed on a sidewall of the deep trench
107
at the portion above the capacitor. A polysilicon layer fills into the deep trench
107
above the capacitor. The polysilicon layer includes a lower portion between the oxide collar
114
and an upper portion
118
which has a contact to the deep trench. An implantation process with sufficient energy is performed is performed to implant ions into the substrate o as to form a buried plate
120
. The buried electrode
120
also has an electric contact on the buried plate
108
. Moreover, the polysilicon layer
116
,
118
are also implanted with dopants.
In
FIG. 1C
, The dopants of the polysilicon layer
116
,
118
can diffuse into the substrate surface to form a diffusion extension region
124
by a thermal process. The diffusion extension region
124
is used for a connection to a source/drain region of metal-oxide semiconductor (MOS) transistor formed later. At this stage, the trench capacitor
108
+
110
+
112
is electrically coupled to the subsequently formed device through the polysilicon layer
116
,
118
and the diffusion extension region
124
. However, the adjacent two trench capacitors are necessary to be isolated, usually, by a shallow trench isolation (STI) structure. Therefore, it is necessary to form an opening
122
. Formation of the opening
122
conventionally needs another photolithography and etching process, so as to properly remove portions of the silicon nitride layer
104
, the pad oxide layer
102
, the substrate
100
, and the polysilicon layer
118
. This needs an additional fabrication of photomask and the associated photoresist layer.
In
FIG. 1D
, a shallow trench isolation structure
126
is formed to fill the shallow trench isolation opening
122
. Remaining portions of the silicon nitride layer
104
and the pad oxide layer
102
are removed. A MOS transistor is then formed, where the source/drain region
130
is coupled to the diffusion region
124
.
In the foregoing conventional method, the STI structure
126
needs the additional photomask, causing more fabrication complexity and higher fabrication cost.
SUMMARY OF THE INVENTION
The invention provides a method for forming a deep trench capacitor under a shallow trench isolation structure. The method uses a photoresist layer with different thickness. Due to the difference of thickness, the mask layer can be patterned also when the photoresist layer is removed. This allows the subsequent etching process can be performed by a self-aligned manner, so as to form a STI opening without a need of extra photomask.
As embodied and broadly described herein, the invention provides a method for forming a deep trench capacitor under a shallow trench isolation structure. The method includes providing a substrate and sequentially forming pad oxide layer, a first mask layer, and a second mask layer over the substrate. Then, a photoresist layer is formed on the second mask layer, where the photoresist layer relatively has a thicker portion and a thinner portion, the thinner portion is located on a predetermined location to be formed an STI structure thereunder. There is a photoresist opening between the thicker portion and the thinner portion in the photoresist layer to expose the second mask layer. An opening is formed under the photoresist opening by etching the second mask layer, the first mask layer, the pad oxide layer, and the substrate. The lower portion of the opening in the substrate is a deep trench. The photoresist layer is removed, wherein the second mask layer under the thinner portion of the photoresist layer is also removed by self-aligned manner.
A deep trench capacitor is formed on the lower portion of the deep trench. A dielectric collar layer is formed above the deep trench capacitor, on the sidewall of the deep trench. A selective growth polysilicon layer is formed to fill the deep trench of the opening and a height of the selective growth polysilicon layer is higher than a substrate surface. A first self-aligned etching process is performed, using the second mask layer as an etching mask, to remove exposed portions of the first mask layer and the pad oxide layer, thereby exposing a portion of the substrate where is to be formed a STI structure therein. A second self-aligned etching process is performed, using the second mask layer as an etching mask, to simultaneously etch the selective growth polysilicon and the exposed portion of the substrate, whereby a self-aligned STI opening is formed. The self-aligned STI opening exposes a portion of the dielectric collar layer having a contact with the deep trench. Then, a STI structure is formed to fill the STI opening.
In the foregoing, due to different thickness of the photoresist layer, the portion of the second mask layer under the thinner portion is also removed to expose the first mask layer. In the subsequent etching process the second mask layer to the first mask layer can be distinguished by the etching selectivity. This allows the self-aligned etching process to be performed. Moreover, since the height of the selective growth polysilicon layer in the opening is higher than the substrate surface, a STI opening with the profile can be self-aligned etched.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6001684 (1999-12-01), Shen
patent: 6037210 (2000-03-01), Leas
patent: 6100130 (2000-08-01), Iba et al.
patent: 6140175 (2000-10-01), Kleinhenz et al.
patent: 5-136368- (1993-06-01), None
Lee Chiu-Te
Wu Der-Yuan
Chaudhari Chandra
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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