Method for forming capacitor

Details Method for forming capacitor Method for forming capacitor

2002-03-14

2002-10-29

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S398000

Reexamination Certificate

active

06472269

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-47489, filed on Oct. 29, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a capacitor of a semiconductor device that can prevent an occurrence of operational failure caused by a cleaning process, and can simplify the operational processes when the capacitor is fabricated by the application of a hemispherical grain (hereinafter referred to as HSG).
In accordance with a general trend of high integration in semiconductor devices, continuous efforts have been made to decrease a region occupied by a capacitor in an identical area of the device, while simultaneously securing its large capacitance. This will allow a reduction in the size of a chip with large memory capacity. Currently, semiconductor devices are being fabricated using a method in which an HSG process is performed to maximize the effective area for DRAM capacitors, while minimizing it's actual area.
FIG. 1
is a cross-sectional view illustrating a capacitor fabricated by a conventional method. With reference to
FIG. 1
, the capacitor is constructed in a deposition structure sequentially comprising: a semiconductor substrate
10
, an insulating interlayer
20
, a lower electrode
30
, an HSG
40
. a dielectric layer
50
, and an upper electrode
60
.
The insulating interlayer
20
is formed on the semiconductor substrate
10
, and has a buried contact hole (h) formed in it. The lower electrode
30
is formed on the insulating interlayer
20
and in the contact hole (h). The HSG
40
is formed on the lower electrode
30
, and the dielectric layer
50
is formed on the HSG
40
and the lower electrode
30
to separate them from the upper electrode.
The capacitor described above is fabricated as shown in the operational block diagram of
FIG. 2
as follows.
An insulating interlayer
20
is initially formed on a semiconductor substrate
10
(step
100
).
A buried contact hole (h) is them formed in the insulating interlayer
20
(step
105
). This is accomplished by forming a mask pattern (not shown) on the insulating layer
20
to restrict a lower electrode forming part, and using the mask pattern to etch the insulating interlayer
20
to expose a predetermined portion of the surface of the substrate
10
.
An electrode material, e.g., a high density P-type impurity, is then doped into the exposed surface of the substrate
10
and insulating interlayer
20
to form an amorphous polysilicon layer (step
110
). This is done to fill up the inner portion of the contact hole (h). After this, another mask pattern that restricts a lower electrode forming part is applied to selectively etch the polysilicon layer. As a result of this, the polysilicon lower electrode
30
is formed over a predetermined portion of the insulating interlayer
20
and in the contact hole (h).
A first cleaning process is then performed to eliminate all of the particles (e.g., contaminants like natural oxide layer) remaining on the resultant structure, including the completely formed lower electrode
30
(step
115
).
An HSG
40
is then selectively grown on the exposed surface of the lower electrode
30
to maximize an area of the capacitor (step
120
).
Then, a second cleaning process is performed to eliminate all of the particles remaining on the resultant structure after the HSG
40
is formed (step
125
).
In order to increase the surface density of the HSG
40
, a PH
3
impurity is then doped into the HSG
106
for about 180 minutes under an operational condition of “high temperature and low pressure” (step
130
).
Next, a third cleaning process is performed to eliminate all of the particles remaining on the resultant structure after the PH
3
doping is completed (step
135
).
A dielectric layer
50
is then deposited onto the insulating interlayer
20
, the lower electrode
30
, and the HSG
40
(step
140
).
Then, a doped amorphous polysilicon layer is formed on the dielectric layer
50
, to be used as an upper electrode (step
145
). The doped amorphous polysilicon layer is preferably doped with a high density P-type impurity. The doped amorphous polysilicon layer is then selectively etched using a mask pattern that restricts an upper electrode forming part to thereby form the polysilicon lower electrode
60
. In this way all of the operational processes for fabricating the capacitor are performed.
However, if a capacitor is fabricated by the aforementioned method, a problem arises. The processes for doping PH
3
and forming the dielectric layer should be separately performed in different chambers or facilities, followed by cleaning steps after the completion of each level of the fabricating processes. This can substantially complicate all the fabrication processes.
Furthermore, as the integration of a semiconductor device increases, the cell area decreases and so the gap between lower electrodes decreases. In the third cleaning process, after the PH
3
doping, a part of the silicon lumps stuck onto the lower electrode
30
by the HSG process may fall off the surface of the lower electrode
30
onto the insulating interlayer
20
formed between two capacitors. If this happens, the fallen silicon lump can form a bridge between two capacitors, which can bring about the operational failure of the two capacitors. As a result of this, there has been an urgent demand to solve the aforementioned problems.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to solve the problems set forth above and to provide a method for fabricating a capacitor of a semiconductor device, in which processes for doping PH
3
and forming a dielectric layer followed by growth of HSG are continuously performed in a sheet fed chamber without breaking up the chamber's its vacuum state. This is done to insure that there will be no occurrence of an operational failure resulting from the cleaning step that follows the process of doping PH
3
. As a result, this prevents an operational failure of the capacitor and simplifies the processes of fabricating the capacitor.
In order to accomplish the aforementioned object, a method is provided in accordance with an embodiment of the present invention comprising forming an insulating interlayer over a semiconductor substrate; forming a buried contact hole in the insulating layer to expose a predetermined portion of the semiconductor substrate; forming a lower electrode over the insulating interlayer and in the buried contact hole; performing a first cleaning process on the insulating layer and lower electrode; growing a hemispherical grain (HSG) on an exposed portion of the lower electrode; performing a second cleaning process on the lower electrode and the HSG; doping an impurity into the HSG; and forming a dielectric layer over HSG and the lower electrode. The doping of an impurity into the HSG and the forming of a dielectric layer are performed in a single process chamber without breaking up of a vacuum state of the chamber.
The impurity is preferably PH
3
. The chamber is preferably a sheet fed chamber. The method for fabricating a capacitor may further comprise forming an upper electrode over the dielectric layer.
In order to accomplish the aforementioned object, there is also provided a method in accordance with another embodiment of the present invention comprising forming an insulating interlayer over a semiconductor substrate; forming a buried contact hole in the insulating layer that exposes a predetermined portion of the semiconductor substrate; forming a lower electrode over the insulating interlayer and in the buried contact hole; performing a cleaning process on the lower electrode and the insulating interlayer; growing a hemispherical grain (HSG) on an exposed portion of the lower electrode; doping an impurity into the HSG; and forming a dielectric layer over the HSG and the lower electrode. The gr

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