Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-02-17
2001-10-09
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S382000, C438S384000
Reexamination Certificate
active
06300180
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to metal oxide semiconductor static random access memory (SRAM) devices having load transistors, and to the manufacture thereof.
DESCRIPTION OF THE RELATED ART
Metal oxide semiconductor (MOS) components are used to provide random access memory (RAM) devices operating in a static mode. These static RAM (SRAM) devices are typically implemented as a 4-transistor cell having two resistors or as a 6-transistor cell. An example of a 4-transistor SRAM cell is shown in
FIG. 1A
, with MOS transistors Q
1
and Q
4
providing the gating or addressing of the SRAM cell and MOS transistors Q
2
and Q
3
in combination with the load resistors R
1
and R
2
forming a bistable unit for storing a digital value. To read data from the SRAM cell in
FIG. 1A
, an address signal is supplied to set the gates of Q
1
and Q
4
to V
DD
(logic “1” for NMOS). If a “1” is stored in the SRAM cell, then Q
3
is on and Q
2
is off so that node N
2
is at 0 volts and node N
1
is at V
DD
. In order to write a “1” into the SRAM cell, an address signal is supplied that sets the gates of Q
1
and Q
4
to V
DD
, the data line B is grounded and the data line A set to V
DD
. Current now flows into the data line B through R
2
and Q
4
to effectively ground the node N
2
. This cuts off Q
2
, and node N
1
rises to V
DD
. Consequently, Q
3
is held on and N
2
is maintained at 0 volts. When the address signal is removed, turning off Q
1
and Q
4
, a “1” has been written into the selected memory cell. A “0” may be read from and written to the SCRAM cell in a similar manner.
In the 4-transistor cell shown in
FIG. 1A
, polysilicon (poly) is typically used to form the resistor loads R
1
and R
2
. The MOS transistors of the 4-transistor cell are traditionally formed by doping the gates using a diffusion technique known as POCL
3
.
Polysilicon resistors are intrinsic (i.e., undoped) devices. However, the MOS transistor gate is POCL
3
doped. Hence, the polysilicon resistors are typically implemented in a second polysilicon layer folded on top of the NMOS transistors. Thus, the 4-transistor cell of the prior art requires more than one polysilicon layer to form the polysilicon resistors.
FIG. 1B
depicts a conventional layout of the 4-transistor cell. Each of the NMOS transistors Q
1
-Q
4
comprises an active layer
10
for source, drain, and channel regions, and each gate comprises a polysilicon body
12
formed from a first polysilicon layer. Resistors R
1
and R
2
are formed by depositing a second polysilicon layer that on top of the first polysilicon layer with an insulating layer separating the two polysilicon layers. Resistors R
1
and R
2
are then formed from polysilicon bodies
14
patterned from the second polysilicon layer. The use of more than one polysilicon layer results in a relatively complex structure that limits the number of available fabrication techniques. For example, the two poly-layer SRAM cell cannot be fabricated using existing application-specific integrated circuit (ASIC) processes or single poly logic processes.
SRAM cells having six MOS transistors have been used as an alternative to the 4-transistor cell.
FIG. 2A
is a circuit diagram of a 6-transistor SRAM cell, and
FIG. 2B
is a typical layout of the 6-transistor SRAM cell. The conventional 6-transistor SRAM cell typically includes four NMOS transistors Q
1
-Q
4
, and two PMOS transistors Q
5
-Q
6
operating as load transistors.
An advantage of the 6-transistor SRAM cell is that it can be formed using a single polysilicon layer. Hence, 6-transistor SRAM cells are typically used in logic and ASIC designs in order to accommodate existing logic and ASIC processes. In addition, 6-transistor SRAM cells have a lower standby current and lower sensitivity to alpha (&agr;) particles than 4-transistor cells. However, the 6-transistor cell is typically two to three times larger than the above-described 4-transistor cell. Moreover, the 6-transistor cell, with its combined use of NMOS and PMOS transistors, is susceptible to latch-up.
Thus, the existing 4-transistor SRAM cell requires complex manufacturing processes to obtain the double poly layer structure. Hence, these cells cannot be used in single poly logic designs or ASIC designs because single poly logic and ASIC fabrication processes cannot manufacture the multiple poly layer SRAM cells. Moreover, 4-transistor fabrication techniques are expensive and suffer from probability of defects due to increased complexity.
SRAM cells in logic and ASIC designs are 6-transistor cells in order to fit the existing logic and ASIC fabrication processes. Since the 6-transistor SRAM cell requires substantial silicon “real estate,” the density of logic and ASIC designs is limited.
SUMMARY OF THE INVENTION
In view of the foregoing, there is a need for a 4-transistor SRAM cell that can be formed using a single layer of polysilicon (poly).
There is also a need for a method of forming a SRAM cell of MOS transistors with a minimum degree of complexity.
There is also a need for a 4-transistor SRAM cell that provides an improved yield and reliability.
There is also a need for a 4-transistor SRAM cell that is the same size or smaller than conventional double poly layer SRAM cells, using simplified processing.
There is also a need for a 4-transistor SRAM cell that can be implemented in existing single poly logic and ASIC designs, fabricated by single poly logic and ASIC processes.
These and other needs are met by the present invention, which provides an SRAM cell having a plurality of metal oxide semiconductor transistors and load resistors arranged to minimize complexity during the fabrication process, by providing a 4-transistor SRAM cell that avoids multiple polysilicon layers. As a result, the SRAM cell of the present invention can be manufactured using existing sub-micron logic processes and ASIC processes.
According to the invention, a static random access memory (SRAM) cell formed on a semiconductor substrate comprises metal oxide semiconductor (MOS) transistors each comprising source and drain regions formed of a first impurity in the substrate, and a conductive gate formed of a polysilicon layer overlying and between the source and drain regions. At least one load resistor formed from the polysilicon layer is electrically connected to at least one of the MOS transistors. By using the same polysilicon layer to form the MOS transistor gates and the poly resistors, the invention enables implementation of a 4-transistor SRAM cell in submicron logic or ASIC processing. Hence, the size of the implemented logic circuit or ASIC is reduced.
Further according to the present invention, the MOS transistors are connected to each other by a local interconnect structure formed from a reaction between deposited silicon and a refractory metal silicide. The MOS transistors have silicide regions formed from exposed source and drain regions, and polycide regions formed from the polysilicon gate. Polycide regions are also formed on the poly resistors to electrically connect the resistors to the MOS transistors. Thus, the local interconnect structure connects the MOS transistors and the poly resistors together by electrically connecting the respective silicide and polycide regions.
The present invention also provides a method for forming a SRAM cell device having a single poly-layer resistor. The method comprises the steps of forming a polysilicon pattern from polysilicon deposited on a field-oxidized silicon substrate, whereby the polysilicon pattern includes polysilicon bodies used in forming MOS transistor gates and poly resistors. The device is then implanted at portions of the field-oxidized silicon substrate with a first impurity to form source and drain regions for the MOS transistors. An oxide layer pattern is then formed exposing portions of the implanted field-oxidized silicon substrate and the polysilicon pattern. A refractory metal silicide is deposited on the oxide layer pattern, and an amorphous silicon pattern formed on the deposited refractory metal silicide. Heat
Chang Kuang-Yeh
Liu Yowjuang W.
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
Thomas Toniae M.
LandOfFree
Method for forming an integrated circuit having improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming an integrated circuit having improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming an integrated circuit having improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2577875