Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-06-19
2007-06-19
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C216S046000, C216S067000, C216S069000, C216S070000, C438S637000, C438S638000, C438S643000, C438S646000, C438S668000, C438S696000, C438S697000, C438S708000, C438S712000, C438S714000, C438S719000, C438S720000, C438S730000
Reexamination Certificate
active
10871102
ABSTRACT:
A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.
REFERENCES:
patent: 6372638 (2002-04-01), Rodriguez et al.
patent: 6410424 (2002-06-01), Tsai et al.
patent: 6613683 (2003-09-01), Hwangbo et al.
patent: 6635576 (2003-10-01), Liu et al.
S.Wolf, Silicon Processing for the VLSI Era, vol. IV, Lattice Press, (2002), pp. 245, 249-251 and 502.
S.Wolf, Silicon Processing for the VLSI Era, vol. I, Lattice Press (1986), pp. 554 and 555.
Chang Chia-Der
Chang Yu-Ching
Chou Chien-Chih
Yen Yi-Tung
Angadi Maki
Norton Nadine
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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