Method for forming a trench isolation structure in an integrated

Details Method for forming a trench isolation structure in an integrated Method for forming a trench isolation structure in an integrated

1998-09-10

2000-08-22

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438437, 438692, 438696, 438702, H01L 21762

Patent

active

061071439

ABSTRACT:
A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a sidewall-insulating layer along the sidewall and bottom of the trench, and depositing a trench-insulating layer in the trench and over the semiconductor substrate. The sidewall-insulating layer is formed to have a lower etch rate than the trench-insulating layer. As a result of this difference in etch rates, the sidewall-insulating layer is not damaged too much during wet etching processes that take place during the later part of manufacture. This makes the interface between the substrate, sidewall-insulating layer, and gate oxide more reliable. The difference in etching rate can be obtained by keeping an annealing process used in later processing below a threshold temperature so that the etch rate of the trench-isolating layer does fall too low. The difference in etching rate can also be obtained by using different materials for the sidewall-isolating layer and the trench-isolating layer, or by using multiple annealing processes.

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T. Park et al., "Coprrelation of the Gate Oxide Reliability with the Densification Condition of the Trench Filling CVD Oxide in Deep Sub-micron Si Devices", Source Unknown, date unknown.
K. Ishimaru et al., "Michanical Stress Induced MOSFET Punch-through and Process Optimization for Deep Submicron TEOS-O3 filled STI Device" 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 123-124.
Tai-su Park et al., "Correlation between Gate Oxide Reliability and the Profile of the Trench Top Corner in Shallow Trench Isolation (STI)" 1996 IEEE, pp. 747-750.

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