Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-01
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000, C438S424000
Reexamination Certificate
active
06258676
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a shallow trench isolation using HDP silicon oxynitride.
2) Description of the Prior Art
As the density of components on integrated circuits increases, effective isolation between circuits and/or devices becomes increasingly important. Typically, isolation of circuit components in modern integrated circuit technology takes the form of shallow trenches which are etched into the semiconductor substrate and filled with an insulating material, usually silicon dioxide. These trenches filled with insulating material are generally referred to in the art as a shallow trench isolation (STI) or shallow trench isolation region.
Because of the complex topography of modem integrated circuits, a problem is often encountered in achieving a uniform fill of insulating material in the trenches. This is especially true when trenches of varying widths are used. In order to address this problem, a number of methods have been developed for filling STI trenches with insulating materials and for planarizing the resulting structures in order to obtain a uniform planer topography. STI filling methods include chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition, which take advantage of the fact that insulating material can be transported as a vapor to a surface and deposited thereon. Additionally, sputtering techniques or thermal techniques which grow oxide layers directly in the trenches (e.g. LOCOS) are also useful for filling STI trenches. Planarization schemes such as resist etch-back, reactive ion etching, and chemical mechanical polishing processes are employed, individually or in combination, to planarize the surface of the semiconductor substrate following formation of an insulating layer.
Although all of the above-mentioned STI fill methods have been used successfully for filling both narrow and wide trenches in semiconductor substrates, voids can occur in the insulating material of the STI due to imperfect filling conditions. Hence, there exists a need for a gapless filling technique for STI trenches in modern semiconductor fabrication. In addition to the need for gapless trench filling process, there exists a problem of planarizing the resulting structure. A highly planarized surface topography is desirable since it allows for the deposition of additional integrated circuit components and permits greater device density.
Weigand (U.S. Pat. No. 5,851,899) discloses a method for voidless gapfill and planarization, using high density plasma-chemical vapor deposition (HDP-CVD) to fill the trenches, and using a reverse mask etch followed by a short CMP process to planarize the resulting silicon dioxide STI structure.
However, the silicon dioxide STI structures formed by the method disclosed by Weigand suffer from two problems as the result of subsequent processing steps common to modern semiconductor fabrication. Exposed portions of the silicon dioxide STI structure can be etched by a HF etching process which is commonly used for etching through adjacent silicon oxide layers to form contacts (such as for source and drain regions), and to form suicides, for devices (such as transistors) in modern semiconductor fabrication. The etching of the silicon dioxide STI structure can cause recesses in the STI structure which can cause leakage. Also, thermal stress, due to high temperature processing, such as source and drain ion drive-in, can cause leakage problems in silicon dioxide STI structures.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,851,899 (Wiegand) shows a method of forming a shallow trench isolation by filling a trench with HDP silicon dioxide, performing a reverse mask etch to reduce the thickness of the HDP silicon dioxide over active areas, and performing a short chemical mechanical polishing process.
U.S. Pat. No. 5,753,562 (Kim) shows a method of forming a shallow trench isolation by forming oxide spacers on the sidewalls of a trench, forming a nitride layer, forming a second oxide layer, and planarizing.
U.S. Pat. No. 5,721,173 (Yano et al.) shows a HDP silicon dioxide gap fill layer and planarization process using a polysilicon etch barrier.
U.S. Pat. No. 5,258,332 (Horioka et al.) discloses a method for forming a trench with rounded corners using fluorine and oxygen chemical dry etching process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a shallow trench isolation which is resistant to recessed thickness caused by subsequent processing, particularly HF etching.
It is another object of the present invention to provide a method for forming a shallow trench isolation which is resistant to thermal stress induced leakage.
It is another object of the present invention to provide a method for forming a shallow trench isolation which is resistant to HF etching and thermal stress by forming a liner oxide layer followed by a HDP silicon oxynitride (SiO
x
N
y
) layer in a trench having rounded corners, wherein the liner oxide layer is used as a stop layer for a HDP silicon oxynitride chemical mechanical polishing process.
It is yet another object of the present invention to provide a method for forming a shallow trench isolation without first forming a pad oxide/silicon nitride stack over the active areas of the substrate.
To accomplish the above objectives, the present invention provides a method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad oxide layer, and the semiconductor substrate are patterned to form a trench having rounded corners in the isolation area. A liner oxide layer is formed over the semiconductor substrate, and a gap fill layer is formed on the liner oxide layer. An important feature of the invention is that the gap fill layer is composed of silicon oxynitride formed using a high density plasma chemical vapor deposition process. A portion of the gap fill layer over the active area is removed, and the gap fill layer is planarized with a chemical mechanical polishing process using the liner oxide layer as chemical mechanical polishing stop.
The main steps of a method for forming a shallow trench isolation using HDP silicon nitride according to the present invention are summarized in table 1.
TABLE 1
FIGS.
PROCESS STEP
1-2
form a tranch having rounded corners
3
grow a liner oxide layer
4
deposit a HDP silicon oxynitride
5
reverse mask etch HDP silicon oxynitride over active areas
6
CMP using liner oxide layer as a CMP stop
7
remove liner oxide layer
The present invention provides considerable improvement over the prior art. The HDP silicon oxynitride gap fill layer provides good gap filling properties like HDP oxide, but the HDP silicon oxynitride is also resistant to damage by HF etching and high temperature processing. The use of the liner oxide layer as a CMP stop provides effective planarization of the gap fill layer. Also, since the CMP is stopped above the level of the semiconductor substrate, the residual silicon oxynitride overlying the active areas can be removed using an H
3
PO
4
dip without recessing the STI structure.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5753562 (1998-05-
Chew Peter
Lee Kong Hean
Chartered Semiconductor Manufacturing Ltd.
Jones Josetta I.
Niebling John F.
Pike Rosemary L. S.
Saile George O.
LandOfFree
Method for forming a shallow trench isolation using HDP... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a shallow trench isolation using HDP..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a shallow trench isolation using HDP... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2452016