Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-01
2001-04-03
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S307000, C438S595000
Reexamination Certificate
active
06211024
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form source/drain regions, for metal oxide semiconductor field effect, (MOSFET), devices, via ion implantation and rapid thermal anneal, (RTA), procedures.
(2) Description of Prior Art
The use of sub-micron MOSFET devices, for logic as well as memory applications, has focused attention on the methods used to form shallow MOSFET source/drain regions. Conventional ion implantation procedures have been used to place a specific dose of implanted species, at a specific location in the region of a semiconductor substrate used for the source/drain regions. A high temperature anneal procedure is then used to distribute the implanted ions, resulting in the desired source/drain region. These procedures however, when used for sub-micron MOSFET devices, (or devices with channel lengths less than 0.25 um), can result in undesired source/drain—substrate leakages, due to crystal defects in the semiconductor substrate. The crystal defects can result from a high, source/drain, ion implantation dose, concentrated at one specific region in the semiconductor substrate. In addition a subsequent anneal procedure, used to activate the implanted species, has to be performed at a temperature high enough to distribute the implanted species, from the specific implanted location in the substrate, throughout the source/drain region. This high temperature anneal procedure results in unwanted dopant movement, at other locations in the MOSFET device, as well as aggravating the crystal defect formation.
This invention will describe a combination of processes, comprised of a novel ion implantation procedure, followed by a low temperature RTA procedure, used to create shallow source/drain regions, for sub-micron MOSFET devices. The ion implantation procedure features the use of a sequence of ion implantation steps, each performed at a specific energy and a specific dose, thus avoiding the placement of one large implanted dose, in one location of the subsequent source/drain region, reducing the risk of crystal damage. The placement of implanted species in several locations of the subsequent shallow source/drain region, relaxes the RTA temperature needed for distribution of the implanted species, also reducing the risk of crystal defect formation. Prior art, such as Gardner et al, in U.S. Pat. No. 5,793,090, describe a sequence of ion implantation steps used to form a source/drain region, however that prior art does not feature the unique combination of implant doses, or the use of a low temperature anneal procedure, used in this present invention.
SUMMARY OF THE INVENTION
It is an object of this invention to form a shallow source/drain region, for a sub-micron MOSFET device, via ion implantation and RTA procedures.
It is another object of this invention to use a sequence of ion implantation steps, to place implanted species at specific locations of a subsequent source/drain region, with the highest concentration of implanted species initially implanted deeper in the source/drain region than the lowest concentration of implanted species.
It is still another object of this invention to use a RTA procedure, performed at a reduced temperature, to uniformly distribute the ion implanted species, resulting in a uniform dopant concentration for the shallow source/drain region, without crystal defect formation.
In accordance with the present invention a method of forming a shallow source/drain region for a sub-micron, MOSFET device, featuring the use of a sequence of ion implantation steps, each performed at a specific energy and a specific dose, and featuring a low temperature RTA procedure, used to uniformly distribute the ion implanted species, has been developed. After creation of a gate structure, on an underlying gate insulator layer, a lightly doped source/drain region is formed in a region of the semiconductor substrate, not covered by the gate structure, followed by the formation of insulator spacers on the sides of the gate structure. A sequence of ion implantation procedures is next performed, placing specific concentrations of implanted ions at specific depths, in a region of the semiconductor substrate not covered by the gate structure, or by the insulator spacers. The sequence of ion implantation procedures is comprised of a first ion implantation procedure, placing a first concentration of ion implanted species in a region of the semiconductor substrate; a second ion implantation procedure, placed shallower in the semiconductor substrate than the first ion implantation procedure, and featuring a second concentration of ions, lower in ion concentration than the first ion implantation concentration; and a third ion implantation procedure, placed closest to the surface of the semiconductor substrate, featuring a third concentration of ion implantation species, lower in concentration than the second concentration of ion implanted species. A low temperature, RTA procedure is then employed to distribute the implanted species, resulting in a uniformly doped, shallow source/drain region.
REFERENCES:
patent: 5155369 (1992-10-01), Current
patent: 5719424 (1998-02-01), Ahmad et al.
patent: 5793090 (1998-08-01), Gardner et al.
patent: 5998274 (1999-12-01), Akram et al.
patent: 6096616 (1999-12-01), Nistler et al.
Chou Kou-Yu
Liu Chi-Wen
Ackerman Stephen B.
Chaudhari Chandra
Chen Jack
Saile George O.
Taiwan Semiconductor Manufacturing Company
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