Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-09
2001-12-25
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S672000, C438S647000, C438S629000
Reexamination Certificate
active
06333219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a cell area and a peripheral circuit area, and more particularly, to a method for manufacturing a semiconductor device in which a polysilicon node is formed in a cell area without decreasing the thickness of a gate electrode capping layer formed in a peripheral circuit area.
2. Description of the Related Art
Due to the increased integration density of semiconductor devices having a cell area and a peripheral circuit area, conventional photo-lithographic methods have come to exhibit certain shortcomings. For example, fabrication limitations arise when forming contact holes for a bit line connection plug, which connects an active area (such as a source and a drain) with bit lines. Limitations also arise when forming a storage electrode connection plug, which connects an active area and a storage electrode of a capacitor.
In forming a contact hole, an interlayer insulating layer (e.g., an oxide layer) covers a gate electrode structure, including a spacer formed on a side wall of a gate electrode, and a capping layer formed on the top surface of the gate electrode. The spacer and capping layer are formed of a substance (e.g., nitride) which has a high etching selectivity with respect to the oxide layer.
Active areas between two adjacent spacers are exposed through a self-aligned process. In forming a self-aligned contact hole, an etching process is performed with a peripheral circuit area being masked by a contact-type self-aligned photoresist mask pattern, which exposes a portion of a cell area where the contact hole will be formed. If the contact-type self-aligned photoresist mask pattern is misaligned, a bridging phenomenon may occur in which a bit line contacts other adjacent bit lines, eventually resulting in a short-circuit between the bit lines and a gate electrode under the bit lines. In an attempt to overcome this problem, the contact-type self-aligned photoresist mask pattern may be replaced with a line-type photoresist mask pattern. The line-type photoresist mask pattern exposes an area where a contact hole will be formed and a gate electrode placed on both sides of the area is used.
The contact hole, formed by the line-type photoresist mask pattern, exposes the active area between gate electrodes in the cell area. The photoresist mask pattern is then removed. During this process, the capping layer in the cell area is damaged or reduced in thickness to a depth of 600-700 Å.
After a polysilicon layer is formed on the entire surface of the cell area and the peripheral area, a polysilicon node of a cell is formed of chemical mechanical polishing (CMP). During the CMP process, the capping layers in the cell area and the peripheral area are additionally damaged to depths of about 200 Å and 400-600 Å, respectively.
The decrease in thickness of the capping layer is undesirable and reduces the reliability of the semiconductor devices. During the process for forming self-aligned holes in a peripheral area, the possibility arises of a short circuit between a gate electrode and a bit line connection plug or an interconnection connection plug, or between a gate electrode and a bit line or an interconnection.
SUMMARY OF THE INVENTION
If is an object of the present invention to provide a method of forming a bit line connection plug and a storage electrode connection plug node of a cell area, without decreasing the thickness of a capping layer formed in a peripheral area.
Accordingly, to achieve the above and other objects of the invention, the present invention provides a method of forming a semiconductor device in which a peripheral circuit area of the device is first masked. A self-aligned contact hole is then formed in a cell area of the device, using a capping layer formed on the upper part of a gate electrode formed in the cell area, and a spacer formed along the side walls of the gate electrode. Next, a polysilicon layer is formed on the entire surface of the cell area and the peripheral circuit area. This polysilicon layer is etched twice. A first etch back process is performed using a reactant etching gas having a high etching rate with respect to the polysilicon layer (e.g., a reactant etching gas including Cl
2
gas). The first etch back process on the polysilicon layer is stopped before exposing the top surface of the capping layer in the peripheral circuit area, thereby leaving a thin polysilicon film on the capping layer in the peripheral circuit area. Preferably, the first etch back process is stopped when the thickness of the thin polysilicon film remaining on the capping layer in the peripheral circuit area is about 1000 Å.
A second etch back process is performed on the entire surface of the polysilicon layer to form a polysilicon node filling a self-aligned contact hole in a cell area. In the second etch back process, an etching reactant gas (e.g., HBr gas) is used, which has a high etching selectivity of polysilicon with respect to the capping layer, and does not bring about a loading phenomenon.
In the first and second etch back processes, the polysilicon node is formed in the cell area and the thickness of the capping layer on the top part of the gate electrode in the peripheral circuit area does not decrease. Thus, when a self-aligned contact hole is formed in a peripheral circuit area, a short circuit between the gate electrode and a subsequently formed bit line is avoided.
REFERENCES:
patent: 6271117 (2001-08-01), Cherng
Jeon Jeong-sic
Min Gyung-jin
Park Wan-jae
Samsung Electronics Co,. Ltd.
Tsai Jey
Volentine & Francos, PLLC
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