Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-09-27
2004-10-12
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S587000, C438S761000
Reexamination Certificate
active
06803313
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to fabrication of semiconductor devices, and in particular, to bi-layer hardmasks that include a plasma-enhanced chemical vapor deposition (PECVD) layer such as PECVD silicon oxynitride (SiON).
2. Background Technology
Features of semiconductor devices such as gate lines are typically patterned using a bi-layer structure that serves as a bottom antireflective coating during photoresist patterning, and that further serves as a hardmask during patterning of an underlying patternable layer.
FIG. 1
shows a structure that may be employed in such processing to form a gate line of a MOSFET. As shown in
FIG. 1
, a semiconductor substrate
10
includes isolations
12
that define an area in which a MOSFET is to be formed. A conformal gate insulating layer
14
such as silicon oxide is formed over the substrate
10
and oxides
12
. A gate conductive layer
16
such as polysilicon is deposited over the gate insulating layer
14
and will be patterned to form a gate line. Formed over the gate conductive layer
16
is a bi-layer structure that serves as a bottom antireflective coating (BARC) and as a hardmask for patterning underlying layers. The bi-layer structure includes an amorphous carbon layer
18
and a PECVD SiON capping layer
20
having a thickness of approximately 260 angstroms. The amorphous carbon layer is doped with nitrogen to improve its etch selectivity with respect to the underlying polysilicon
16
. A photoresist mask
22
is formed on the SiON capping layer
20
. The photoresist mask
22
is used to pattern the SiON layer
20
, which in turn is used as a hardmask to pattern the amorphous carbon layer
18
, which in turn is used as a hardmask to pattern a gate line from the polysilicon layer
16
.
As critical dimensions of semiconductor devices shrink, the dimensions of the structures used to pattern those devices are also reduced. In the case of the bi-layer structure of
FIG. 1
, this is seen as a decrease in the thicknesses of the SiON and amorphous carbon components of the bi-layer. At current dimensions, such thinning can produce detrimental effects. One source of detrimental effects is the presence of “pinholes” in the PECVD capping layer. Pinholes are believed to be formed by outgassing from underlying layers during deposition of the PECVD material. For example, when SiON is formed over an amorphous carbon layer, residual hydrogen may be emitted from the amorphous carbon layer. These emissions cause localized non-uniformities in the PECVD deposition plasma, which result in reduced deposition of SiON in the vicinities of the non-uniformities. Pinholes that extend partly or entirely through the SiON layer may form at those locations.
Pinholes are a source of at least two problems. One of these problems is photoresist poisoning. As shown in
FIG. 1
b
, a pinhole
24
enables diffusion of nitrogen dopant from the amorphous carbon layer
18
into an overlying photoresist layer
26
, forming a region of poisoned photoresist
28
. Poisoned photoresist exhibits reduced response to conventional photoresist development chemistries, and as a result, unwanted photoresist bodies may be left behind after development, causing undesired patterning of underlying layers during subsequent processing.
A second problem caused by pinholes is premature etching of the amorphous carbon layer during reworking of photoresist. During typical processing, photoresist layers may be applied over a bi-layer hardmask, patterned, and removed several times. As shown in
FIG. 1
c
, during removal of photoresist, the chemistry used to strip the photoresist may pass through a pinhole and contact the underlying amorphous carbon layer, causing etching of a region
30
in the amorphous carbon. This results in the formation of anomalous patterns in the amorphous carbon that may be transferred to underlying layers during subsequent processing. Such etching has been found to occur even with pinholes that do not extend completely through the SiON layer, a phenomena known as “punch through.”
Accordingly, there is a need for improved semiconductor processing techniques that reduce the detrimental effects of pinholes in PECVD materials.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the invention, a bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct adjacent layers of a PECVD material such as SiON that are formed independently over the amorphous carbon. By independently forming two or more distinct layers of PECVD material, pinholes that are present in the lowermost layer may be prevented from continuing to grow during formation of the overlying layers. Thus by using several layers of PECVD material, the pinhole density at the surface of the PECVD portion of the bi-layer is decreased.
In accordance with one embodiment of the invention, a semiconductor device may be fabricated by forming an amorphous carbon layer over a patternable layer such as polysilicon, and then forming a multi-layer PECVD material over the amorphous carbon. The pinhole density of an upper surface of an upper layer of PECVD material is thus lower than a pinhole density of a lower layer of the PECVD material. A photoresist mask may then be formed over the layers of PECVD material, and a pattern of the photoresist mask may be transferred to the patternable layer. By providing multiple layers of PECVD material, pinhole density is reduced, and so photoresist poisoning and etching of the amorphous carbon layer by photoresist stripping chemistry is reduced.
The layers of PECVD material may be formed either in situ or ex situ. The PECVD material may comprise any of a variety of materials, including silicon oxynitride, silicon carbide, silicon oxide, SiCH, and SiCOH. More than two layers of the PECVD material may be used.
In accordance with another embodiment of the invention, a bi-layer hardmask structure may include multiple distinct layers of PECVD material. Therefore, the bi-layer hardmask may be incorporated into structure formed during fabrication of a semiconductor device, including a substrate comprising a patternable layer, an amorphous carbon layer formed over the patternable layer, and the PECVD material. The PECVD material may include at least a distinct lower layer and a distinct upper layer of PECVD material formed over the amorphous carbon layer, such that the pinhole density of an upper surface of the upper layer is lower than the pinhole density of the lower layer. A photoresist mask may be formed over the upper layer of PECVD material for transferring of a pattern of the photoresist mask to the patternable layer. By providing multiple layers of PECVD material, pinhole density is reduced, and so photoresist poisoning and etching of the amorphous carbon layer by photoresist stripping chemistry is reduced.
The PECVD material may comprise any of a variety of materials, including silicon oxynitride, silicon carbide, silicon oxide, SiCH, and SiCOH. More than two layers of the PECVD material may be used.
REFERENCES:
patent: 5711987 (1998-01-01), Bearinger et al.
patent: 6440878 (2002-08-01), Yang et al.
Gao Pei-Yuan
Huang Richard J.
You Lu
Advanced Micro Devices , Inc.
Foley & Lardner LLP
Pham Long
Weiss Howard
LandOfFree
Method for forming a hardmask employing multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a hardmask employing multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a hardmask employing multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3270389