Method for forming a contact in a semiconductor device

Details Method for forming a contact in a semiconductor device Method for forming a contact in a semiconductor device

1999-05-20

2001-11-20

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S558000, C438S655000

Reexamination Certificate

active

06319785

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 98-19866, filed on May 29, 1998, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method for forming a contact plug in a semiconductor substrate, and more particularly to a method for forming a contact hole with a low contact resistance and a minimum junction leakage.
BACKGROUND OF THE INVENTION
A connection between a conductive region, e.g. an impurity diffusion layer in a semiconductor substrate or a lower level wiring layer, and an upper level wiring layer through a contact hole formed in an interlayer insulating film is an important technique in manufacturing semiconductor devices. Recently, the fabrication of extremely complex, high-density integrated circuits has been made possible through an advance in integrated circuit fabrication technology. This advance in integrated circuit fabrication technology has scaled devices down toward DRAMs in the gigabit range, which have feature sizes of less than 0.15 &mgr;m. In the case of a memory device with an integration density as high as in the gigabits, contact holes inevitably require a high aspect ratio, i.e., a smaller area compared to their depth.
As the aspect ratio of a contact hole increases, however, so too does its contact resistance. To reduce the contact resistance, an ion implanting process is often carried out on the bottom of the contact hole following the formation of the contact hole.
This conventional method for forming a contact is depicted in
FIGS. 1A
to
1
C, which illustrate the process flow in a cross-sectional view. Referring to
FIG. 1A
, a device isolation layer
12
is formed over a p-type semiconductor substrate
10
. An N
+
type impurity diffusion layer
14
is then formed in the p-type semiconductor substrate
10
, and an interlayer dielectric layer
16
is formed over the semiconductor substrate
10
. A contact hole
18
is then opened in the interlayer dielectric layer
16
to expose a portion of the impurity diffusion layer
14
.
Referring to
FIG. 1B
, in order to improve the contact resistance of this contact hole, impurity ions are implanted into the exposed impurity diffusion layer
14
. As is well known, this ions implantation is provided to serve the dual purpose of preventing p-n junction leakage and suppressing any increase in contact resistance. Such an increase in contact resistance may result from substrate damage and the consumption of the impurity diffusion layer caused by over-etching due to contact hole misalignment.
Referring to
FIG. 1C
, a refractory metal layer
20
is deposited in the contact hole and over the interlayer dielectric layer
16
. A portion of refractory metal layer
20
that contacts the exposed substrate
10
and impurity diffusion layer
14
is then transformed into a silicide layer
22
by an annealing process. A barrier metal layer
24
is then deposited in the contact hole and over the refractory metal layer
20
. Finally, the remainder of the contact hole is filled with a wiring metal
26
, which is patterned, along with the refractory metal layer
20
and the barrier metal layer
24
to form a multilayer metal plug.
The annealing is carried out to out-diffuse implanted impurity ions from the impurity diffusion layer
14
into the silicide layer
22
and the portion of the semiconductor substrate
10
initially in contact with the refractory metal layer
20
.
It is noted that the ion implantation is carried out with a high dose of more than 1×10
15
cm
−2
under an implantation angle that is substantially a right angle with respect to the substrate, i.e., with a tilt of about 0°, because of the high aspect ratio of the contact holes. As a result, the actual impurity concentration depth profile is significantly different from a desired concentration depth profile.
FIG. 2
shows an impurity concentration profile in the silicon substrate after impurity ions are implanted according to this conventional method for forming a contact. As seen in
FIG. 2
, the actual impurity concentration depth profile
2
has a deep tail portion beyond the critical depth as compared a to desired concentration depth profile
1
. This makes if difficult to form a shallow junction and consequently aggravates the short channel effect and increases the channelling effect. Furthermore, substrate damage caused by contact over-etching and point defects caused by ion implanting can cause a silicon dislocation loop at the depletion region of the p-n junction region. An example of such a silicon dislocation loop “A” is depicted in
FIG. 3A
, which is a vertical XTEM (X-transmission electron microscopy) micrograph.
FIG. 3B
is a planar SEM (scanning electron microscopy) of a semiconductor substrate having a defect “B” near the edge portion of an interfacing region between an active region and a device isolation region.
In reverse bias, the presence of a silicon dislocation significantly increases the leakage current of the p-n junction by a magnitude of about 10
6
, as compared to a normal junction leakage. This increase in the leakage current results in an unacceptable increase in the standby current of the device.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problem, and it is therefore an object of the invention to provide a method for forming a contact that can minimize implanting damage during an ion implanting process.
It is another object of the invention to provide a method for forming a contact that can minimize junction leakage.
A key feature of the invention is implanting impurity ions into a contact hole following the formation of a silicide on an impurity diffusion layer, i.e., on bottom of the contact hole. This suicide layer serves to block the implanting damage as well as to reduce contact resistance. Any implanting damage is confined within the silicide layer and the implanted impurities out-diffuse into the underlying impurity diffusion layer during subsequent annealing process.
The above and other objects in accordance with the present invention may be realized by forming an impurity diffusion layer in a semiconductor substrate, and then forming an insulating layer over the impurity diffusion layer. The semiconductor substrate preferably has an opposite conductivity type with respect to the impurity diffusion layer. For example, if the semiconductor substrate is p-type, the impurity diffusion layer is n-type.
A contact hole is then opened in the insulating layer to expose the impurity diffusion layer, preferably by a dry etching process. A refractory metal layer such as cobalt or titanium is deposited in the contact hole and over the insulating layer. The portion of the refractory metal layer contacting the impurity diffusion layer is transformed into a silicide layer by annealing. The silicide formation results from reaction between refractory metal and silicon of the substrate. Impurity ions of the same conductivity type as the diffusion layer are then implanted into resulting structure.
The implanting energy is preferably controlled such that the implanting damages are confined within the silicide layer or refractory metal layer. A barrier metal layer such as a titanium nitride layer is deposited in the contact hole and over the refractory metal layer. Finally, the remainder of the contact hole is filled with a wiring metal such as tungsten, aluminum, or copper. Annealing is then performed to out-diffuse the implanted impurities from the silicide layer into the diffusion layer, specifically increasing impurities concentration at the interface between the silicide layer and the diffusion layer.
According to another aspect of the present invention, if the silicide layer is formed to have a thickness greater than 50 nm, the un-reacted refractory metal can be removed, and then impurity ions can be implanted.
According to another aspect of the present invention, the implantation of impurity ions can be carried out following formation of the barrier layer in the conta

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