Method for forming a capacitor with a multiple pillar structure

Details Method for forming a capacitor with a multiple pillar structure Method for forming a capacitor with a multiple pillar structure

1998-07-24

2000-06-06

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438396, 438398, 438947, H01L 218242

Patent

active

060717742

ABSTRACT:
The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.

REFERENCES:
patent: 5213992 (1993-05-01), Lu
patent: 5302540 (1994-04-01), Ko et al.
patent: 5336630 (1994-08-01), Yun et al.
patent: 5427974 (1995-06-01), Lur et al.
patent: 5459095 (1995-10-01), Huang et al.
patent: 5466627 (1995-11-01), Lur et al.
patent: 5492848 (1996-02-01), Lur et al.

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