Method for forming a blocking layer

Details Method for forming a blocking layer Method for forming a blocking layer

2001-10-19

2003-09-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S765000

Reexamination Certificate

active

06620745

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to methods for forming blocking layers and more particularly to a method for forming a blocking layer to reduce a diffusion rate of a chemical species thereby improving a photolithographic process.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density on the chip. One of the limiting factors in the continuing evolution toward the smaller device size and higher density has been the interconnect area needed to route interconnect lines between devices. As a way to overcome such limitation, multilayer interconnection systems with increasingly smaller features have been implemented using shared interconnect lines between two or more layers.
The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, photolithography, etching, and planarization.
One such process for forming a series of interconnected multiple layer devices, for example, is a damascene or dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). One exemplary process, for example, is known in the art as a via-first-trench last process. Typically a conventional photolithographic process using a photoresist layer is first used to pattern and expose an etching mask which is used for etching via openings through an insulating inter-metal dielectric (IMD) layer. Subsequently a similar process is used to define trench openings for metal interconnect lines in an insulating metallization layer that are formed substantially over the via openings. The via opening and trench openings are subsequently filled with metal to form metallization vias and metal interconnect lines, respectively. The surface may then be planarized by conventional techniques, such as chemical mechanical polishing (CMP) to better define the metal interconnect lines and prepare the substrate for further processing.
Referring to
FIG. 1
, typically, an insulating layer (IMD)
12
layer is formed over a metallization layer
10
. Prior to forming the IMD layer
12
, an etch stop layer
14
A, for example, silicon nitride (SiN) or silicon carbide (SiC) is formed over the metallization layer
10
. Another etch layer stop layer
14
B is then formed over IMD layer
12
. Prior to forming via openings
18
A,
18
B, and
18
C, dielectric anti-reflective coating (DARC) layer
16
is formed over the etching stop layer
14
B prior to depositing a photoresist coating
20
for carrying out a photolithographic process used for patterning and subsequently etching by, for example, a reactive ion etch (RIE) the via openings
18
A,
18
B, and
18
C. The DARC layer
16
reduces the effect of light reflection undesirably exposing the photoresist overlayer
20
used for defining via openings
18
A,
18
B, and
18
C. Light reflection (scattering) from, for example, the IMD layer
12
surface, etching stop layer
14
B surface, and their respective interfaces, can cause undesired light exposure of the overlying photoresist layer
20
during photolithographic masking and patterning steps in the formation of via openings
18
A,
18
B, and
18
C. As a result, upon development and removal of the exposed photoresist the phenomenon of undercutting (removing photoresist exposed by reflected light at the base of the photoresist layer) will detrimentally affect the design integrity of the manufactured device.
As feature sizes in etching process have become increasingly smaller, photolithographic processes have been required to use photoresist activating light (radiation) of smaller wavelength. Typically a deep ultraviolet (DUV) activating light source with wavelength less than about 250, but more typically, from about 193 nm to about 230 nm is used. Exemplary DUV photoresists used, for example, have included, PMMA and polybutene sulfone.
Many processes use a metal nitride as a DARC (dielectric anti-reflective coating) such as silicon oxynitride (SiON), silicon nitride SiN, or titanium nitride TiN. Typically, the method of choice for depositing these metal nitride layers is a CVD process where for example, a metal-organic precursor together with nitrogen (and oxygen in the case of SiON) is deposited on a substrate surface, to form a metal nitride. Silicon oxynitride DARC, has been widely used for DUV (deep ultraviolet) lithography because of its tunable refractive index and high etch selectivity to resist.
One problem affecting DUV photoresist processes has been the interference of residual nitrogen-containing species with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use or application of metal nitride films such as SiN as etch stops and, for example, silicon oxynitride as a DARC. For example, nitrogen radicals created due to the presence of nitrogen containing species, such as amines, interfere, with chemically amplified resists by neutralizing the acid catalyst, and rendering that portion of the photoresist insoluble in the developer. As a result, residual photoresist may a remain on the edges and walls of features, affecting subsequent etching or metal filling processes and altering design constraints.
Another aspect of advances in semiconductor device processing technology that exacerbates the problem is the increasing use of low-k (low dielectric constant)insulating materials that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials have become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. An exemplary low-k material is, for example, carbon doped silicon dioxide (C-oxide) which has a dielectric of about 3 or lower and density of about 1.3 g/cm
3
compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm
3
for silicon dioxides (e.g., un-doped TEOS). A shortcoming of porous low-k materials is that they readily absorb and provide diffusion pathways for chemical species.
As a result, amine and nitrogen-containing species remaining in, for example, a SiON DARC, may readily diffuse into an underlying or overlying IMD layer, thereby becoming potentially available for causing interfering effects with a subsequent photoresist process. The contaminating nitrogen-containing species may diffuse back out of the IMD layer during a photoresist process causing residual photoresist to remain after development thereby altering resist profiles by, for example, remaining deposited on feature edges and sidewalls.
There is therefore a need in the semiconductor processing art to develop a method whereby residual nitrogen-containing species in for example, DARC layers, are prevented from diffusing into insulating materials, for example, IMD layers, especially where the IMD layers include a low-k material.
It is therefore an object of the invention to provide a method whereby residual nitrogen-containing species in for example, DARC layers, are blocked from diffusing into insulating materials, for example, IMD layers, especially where the insulating material is a low-k material while ov

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