Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-08
2001-06-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S304000, C257S408000
Reexamination Certificate
active
06245620
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing method. More particularly, the present invention relates to a method for forming a MOS transistor having a bi-layered spacer.
As semiconductor devices become more highly integrated, there is a need to decrease the size of MOS transistors used for semiconductor devices. This reduction in the size of MOS transistors causes a short channel effect. The short channel effect lowers the reliability of the MOS transistor, due to a hot carrier effect, and degrades the electrical characteristics of the MOS transistor e.g., leakage current characteristics between the source and drain regions. As a result, MOS transistors have increasingly adopted the use of a lightly doped drain (LDD). In order to form a LDD region, it is necessary to form spacers at the side walls of a gate electrode. Also, the gate electrode of the MOS transistor must be formed of a conductive material film containing a metal silicide film having a low resistivity, in order to improve the operation speed of a semiconductor device.
FIGS. 1 through 3
are section views illustrating a related method for forming a MOS transistor.
Referring to
FIG. 1
, a gate dielectric film
3
is formed in a semiconductor substrate
1
, and a polysilicon film
5
, a titanium silicide film
7
and a gate protection film
9
, which form a gate pattern
10
, are stacked in sequence on a predetermined region of the gate dielectric film
3
. The gate protection film
9
is formed as a silicon oxide film or silicon nitride film.
Referring to
FIGS. 2 and 3
, a silicon nitride film
11
having a predetermined thickness is formed over the entire surface of the semiconductor substrate
1
having the gate pattern
10
. Preferably, the silicon nitride film
11
is formed to have a dense film quality in order to increase etching selectivity with respect to other dielectric films such as a silicon oxide film. Thus, the silicon nitride film
11
is formed at a high temperature of 750° C. to 800° C. Here, during the formation of the silicon nitride film
11
, the titanium silicide film
7
is easily oxidized or deformed. Thus, a deformed titanium film
7
a
as shown in
FIG. 2
is formed and simultaneously an undesired dielectric film
7
b
such as titanium oxide film is formed at the side walls of the deformed titanium silicide film
7
a.
As a result, the width of the deformed titanium silicide film
7
a,
which actually contributes to the transfer of an electrical signal is decreased to less than the width of the initial titanium silicide film
7
. As a result of this, the resistance of a gate electrode including the polysilicon film
5
and the deformed titanium silicide film
7
a
increases. Then, the silicon nitride film
11
is anisotropically etched to form spacers
11
a
at the side walls of the gate pattern
10
.
According to the conventional method described above, the silicon nitride film for forming the spacers is formed at a high temperature of 750~800° C., so that the titanium suicide film of the gate electrode is deformed. As a result, the resistance of the gate electrode increases, thereby degrading the operation characteristics of the semiconductor device. Such a phenomenon is serious in a MOS transistor used for a highly integrated semiconductor device, because of the short channel length of the MOS transistor, i.e., the narrow gate electrode of the MOS transistor.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method for forming a MOS transistor suitable for a highly integrated semiconductor device, capable of preventing the width of a gate pattern from decreasing while spacers are formed at side walls of the gate pattern.
To achieve the above objective, there is provided a method of forming a MOS transistor of a semiconductor device, comprising: forming a gate dielectric film over a semiconductor substrate, forming a gate pattern over a predetermined region of the gate dielectric film, forming a first dielectric film over the semiconductor substrate and the gate pattern at a first temperature, forming a second dielectric film over the first dielectric film at a second temperature higher than the first temperature, and anisotropically etching the second and first dielectric films in sequence to form bi-layered spacers on side walls of the gate pattern, the bi-layered spacers each including portions of the first and second dielectric films.
The step of forming a gate pattern may further comprise: forming a conductive film over the gate dielectric film, forming a gate protection film over the conductive film, and forming the gate pattern by patterning the gate protection film and the conductive film in sequence, such that the gate pattern comprises a conductive film pattern and a gate protection film pattern.
The conductive film in the gate pattern may comprises a polysilicon film and a metal silicide film, a polysilicon film and a metal film, or a metal film. The metal silicide film may comprise a material selected from the group consisting of titanium silicide, tungsten silicide, and tantalum silicide. The metal film may comprise a material selected from the group consisting of tungsten, titanium nitride, tantalum, and tungsten nitride.
The gate protection film may comprise a material selected from the group consisting of silicon nitride and silicon oxide.
The step of forming a gate pattern may further comprise: forming a conductive film over the gate dielectric film, and forming the gate pattern by patterning the conductive film. The conductive film may be formed by stacking a polysilicon film and a metal suicide film in sequence over the gate dielectric film.
The first dielectric film preferably comprises silicon nitride formed by plasma-enhanced chemical vapor deposition, and the second dielectric film preferably comprises silicon nitride formed by low-pressure chemical vapor deposition.
The first temperature is preferably chosen to be below a temperature at which the gate pattern will deform, e.g., a temperature lower than 500° C. The second temperature is higher than the first temperature and is preferably between 750° C. and 800° C.
In the MOS transistor formation method according to the present invention, the first dielectric film is formed at a low temperature at which the conductive film forming the gate pattern, particularly, the metal silicide film or metal film, is not deformed, which prevents a decrease in the cross-section area of the gate electrode. As a result, the low resistance of the gate electrode after the spacers are formed can be maintained, thereby realizing a MOS transistor capable of improving the operation characteristics of a highly integrated semiconductor device.
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patent: 5183771 (1993-02-01), Mitsui et al.
patent: 5198386 (1993-03-01), Gonzalez
patent: 5208472 (1993-05-01), Su et al.
patent: 5714413 (1998-02-01), Brigham et al.
patent: 5925918 (1999-07-01), Wu et al.
patent: 6013547 (2000-01-01), Liaw
patent: 6168955 (1994-06-01), None
Jang Keung-hee
Lee Eun-ha
Jones Volentine, L.L.C.
Le Dung A
Nelms David
Samsung Electronics Co,. Ltd.
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