Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-05-22
2003-02-04
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
06516433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for finding the root causes of the failure of a faulty chip by computer. More specifically, the present invention relates to a method for finding the contribution that the defects on the faulty chip make to the failure of the faulty chip.
2. Description of the Related Art
The purpose of semiconductor processes is to form several chips with electrical functions on a semiconductor wafer. Thus, during fabrication, the semiconductor wafer has several repetitive patterns formed on its surface, each repetitive pattern being a chip. However, inevitably, some unwanted event occurs making some parts of a chip dissimilar with the same places of the other chips. These places with dissimilar patterns are called defects. For example, if one of the operators in the product line touches the surface of the semiconductor wafer, he causes a scratch defect on the surface. If a particle is dropped on the surface of the semiconductor wafer, it become a hard mask preventing the material below from being etched during a subsequent etch process, thus causing a particle defect. Since the defects usually have associated error functions and result in a faulty chip, the yield rate of a production line is decreased. Thus, decreasing defects is very important goal for a semiconductor factory.
However, not all the defects will decrease the yield rate. For example, if a defect has a very small size or is located somewhere unimportant, the chip with this defect may function as well as a chip without this defect. Thus, to improve the yield rate, it is very important to identify which defects contribute to the failure of a faulty chip. Then, engineers will know what kinds of defects decrease the yield rate and take some action to address them. Thus, discovering the relationship between defects and the failure of the chip is the first step to increase the yield rate by removing significant defects.
In order to discover the defects that result in a faulty chip, the method according to the prior art employs computer to compare the location of each defect with each of the regions that are electrically failed on the faulty chip. Only if the location of a defect is within one of the failed regions will the defect be recognized as one of the root causes of the faulty chip. For example, a memory chip can provide a bit map after testing. A bit map marks the memory cells that are electrically failed and points out their locations. Defects are found by scanning during the process flow. Depending on the scanning between different process steps, many defect maps can be obtained to express the defects on the semiconductor wafer. For example, the defect map of metal
1
(M
1
) layer means the defect map obtained by scanning after the pattern definition of M
1
layer. To find out which defects in the defect map of M
1
layer result in a faulty chip, the prior art makes the defect map of M
1
layer overlay with the bit map of the faulty chip. Only if a defect is located at the location of an electrically failed bit is it recognized as a root cause of the failure of the faulty chip. This is called “hitting”. However, the hitting rate for the bit map, being defined as the number of the faulty chips hit divided by the total number of the faulty chips, is as low as 10% in actual practice.
Not all defects affect the function of the regions in which they are located. For example, a memory chip usually comprises a memory array region and a periphery region. The memory array has a large amount of memory cells. The periphery region has the drivers for driving the memory cells in the memory array region. Suppose one defect is located in the region of one driver and causes the driver to fail. In this case, the memory cells that the driver drives also fail. It is obvious that this defect is one of the root causes of the faulty chip. However, the prior art can't provide a way to discover the relationship between the failure of the faulty chip and the defect because the regions of the failed memories don't include the location of the defect. Thus, the prior art can't provide sufficient information for engineers to take proper actions.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for finding the root causes of a faulty chip. The method of the present invention can find more defects that cause a faulty chip than that of the prior art.
Another object of the present invention is to provide useful information for engineers to improve the yield rate of a product line.
The present invention achieves the above-indicated objects by providing a method for finding the root causes of the failure of a faulty chip. The faulty chip is fabricated by a plurality of processes. The faulty chip comprises at least one defect detected after one of the processes. The defect is characterized by at least one characteristic. The faulty chip is tested to identify at least one real failure region that is electrically failed. The method can be performed by a computer. First, the method performs a defect-to-failure matching step according to the characteristic of each defect to respectively generate a predicted failure region that is predicted to be electrically failed due to the defect. Second, the present invention compares the predicted failure region of each defect with the real failure region. If the predicted failure generated from the defect is located in the real failure region, then the defect is interpreted as one of the root causes of the failure of the faulty chip.
The present invention further provides another method for finding the root causes of the failure of a faulty chip. The faulty chip is fabricated by a plurality of processes. The faulty chip comprises at least one defect that is detected after one of the processes. The defect is characterized by at least one characteristic. The faulty chip is tested to identify at least one real failure region that is electrically failed. The method can be performed by a computer and comprises the following steps. First, the method performs a pattern-recognizing step to characterize the real failure region by a failure range and a failure type. Second, the method performs a failure-to-defect matching step to generate at least one predicted characteristic range according to the failure range and the failure type of the real failure region. Third, the method compares the characteristic of the defect with the predicted characteristic range. If the characteristic of the defect is within the predicted characteristic range, then the defect is interpreted as one of the root causes of the failure of the faulty chip.
In the preferred embodiment, the characteristic of the defect comprises a defect location, a defect size and a defect type. The predicted characteristic range comprises a predicted defect region, a predicted defect size range and a predicted defect type.
The advantage of the method of the present invention is its ability to find more defects that affect the function of the faulty chip than the method of the prior art since the present invention simultaneously considers the defect size, the defect location and the defect type. Thus, the present invention provides useful information for engineers to improve the yield rate of a product line.
REFERENCES:
patent: 5777901 (1998-07-01), Berezin et al.
patent: 5822218 (1998-10-01), Moosa et al.
patent: 6096093 (2000-08-01), Caywood et al.
patent: 6202181 (2001-03-01), Ferguson et al.
patent: 6324481 (2001-11-01), Atchison et al.
Darby & Darby
Promos Technologies Inc.
Ton David
LandOfFree
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