Method for filling via holes in a semiconductor layer structure

Details Method for filling via holes in a semiconductor layer structure Method for filling via holes in a semiconductor layer structure

1994-08-11

1995-12-12

Bowers, Jr., Charles L.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566491, 216 17, 216 18, 216 19, 216 39, 437228, 437203, B44C 122

Patent

active

054746515

ABSTRACT:
For filling via holes that extend onto interconnects to be contacted in a semiconductor layer structure, the interconnects are connected to a conductive layer through auxiliary via holes. The via holes are filled with metal by electro-deposition, whereby the interconnects are wired as a cooperating electrode in an electrolyte via an auxiliary contact to the conductive layer. Subsequently, the conductive layer is removed.

REFERENCES:
patent: 4888087 (1989-12-01), Moslehi et al.
Three-Dimensional ICs Project (Fiscal 1981-1990), Research and Development Assocation for Future Electron Devices, F.E.D., Tokyo, 1991, Chapter 2.1.
J. Electrochem. Soc., vol. 136, No. 1, Jan., 1989; The Electro-Chemical Society, Inc.; Edward K. Yung et al "Plating of Copper Into Through-Holes and Vias", pp. 206-215.

Affiliated with

Also associated with

Rating

Method for filling via holes in a semiconductor layer structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for filling via holes in a semiconductor layer structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for filling via holes in a semiconductor layer structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1357652