Dynamic random access memory with dummy word lines connected to

Details Dynamic random access memory with dummy word lines connected to Dynamic random access memory with dummy word lines connected to

1992-03-25

1993-10-19

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 36518909, 365202, 365203, G11C 11407

Patent

active

052552357

ABSTRACT:
A dynamic random access memory (DRAM) having a plurality of word lines and a plurality of bit line pairs comprises circuitry for applying an equalizing potential to either one or the other bit line of the paired bit lines to equalize (1) a first difference between a first potential and a second potential and (2) a second difference between the first potential and a third potential, for balanced read out of the paired bit lines. The first potential appears on a reference bit line paired with a bit line connected to a memory cell selected by an external address prior to sensing thereof, the second potential appears on the bit line when the selected memory cell contains "H" level data and the third potential appears on the bit line when the selected memory cell contains "L" level data. Each bit line pair has circuitry for adjusting bit line potentials consisting of a pair of capacitors having their electrodes connected to respective bit lines of an associated bit line pair in a corresponding column, and a pair of dummy word lines running parallel to the plurality of word lines, connected to respective other electrodes of the pair of capacitors. When a memory cell, connected to a bit line in a bit line pair, is selected, the potential of a dummy word line capacitively coupled to the other bit line in the bit line pair is rendered active before a sense amplifier is made active for a sensing operation.

REFERENCES:
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patent: 4792922 (1988-12-01), Mimoto et al.
patent: 4799196 (1989-01-01), Takemae
Saito et al., "A 1MB CMOS DRAM With Fast Page and Static Column Modes", IEEE Inter. Solid State Circuits Conference, Digest of Technical Papers, Feb. 15, 1985, pp. 252-253.
Suzuki et al., "A 128K Word.times.8 bit Dynamic RAM", IEEE Journal of Solid State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 624-626.
Chalk, "Noise Reduction by Partial Balancing", IBM Tech. Disc. Bull. vol. 10, No. 1, Jun. 1967, p. 40.

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